hdl/top/sfpga_bootloader: fixed confusing comment about 62.5 MHz system clock

ea79f9a6 · Tomasz Wlostowski · 59f2605e · ea79f9a6
Commit ea79f9a6 authored Jan 24, 2014 by Tomasz Wlostowski
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svec_sfpga_top.vhd hdl/top/sfpga_bootloader/svec_sfpga_top.vhd +1 -1

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--- a/hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
+++ b/hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
@@ -224,7 +224,7 @@ architecture rtl of svec_sfpga_top is
  signal vme_idle                                   : std_logic;
 begin
-- PLL for producing 62.5 MHz system clock (clk_sys) from a 20 MHz reference.
+-- PLL for producing 83.3 MHz system clock (clk_sys) from a 20 MHz reference.
  U_Sys_clk_pll : PLL_BASE
    generic map (
      BANDWIDTH          => "OPTIMIZED",