top: updated ISE projects to use latest versions of submodules (general-cores &…

top: updated ISE projects to use latest versions of submodules (general-cores & vme64x-core). Added synthesis descriptor in the golden bitstream.

top: updated ISE projects to use latest versions of submodules (general-cores &…
top: updated ISE projects to use latest versions of submodules (general-cores & vme64x-core). Added synthesis descriptor in the golden bitstream.
daf244bf · Tomasz Wlostowski · 3ddb956e · daf244bf · daf244bf · daf244bf
Commit daf244bf authored Feb 04, 2014 by Tomasz Wlostowski
7 changed files
--- a/hdl/.gitignore
+++ b/hdl/.gitignore
@@ -19,4 +19,11 @@ doc/
 *.o
 *.bin
 *.elf
 Makefile
\ No newline at end of file
+Backup*.cdr
+*.cmd
+*.log
+*.htm
+*.html
+*.vmf
+*.bit
--- a/hdl/syn/golden/svec_top.xise
+++ b/hdl/syn/golden/svec_top.xise
--- a/hdl/syn/sfpga_bootloader/svec_sfpga.xise
+++ b/hdl/syn/sfpga_bootloader/svec_sfpga.xise
--- a/hdl/top/golden/Manifest.py
+++ b/hdl/top/golden/Manifest.py
-files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd" ]
+files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd", "synthesis_descriptor.vhd" ]
 fetchto = "../../ip_cores"

--- a/hdl/top/golden/svec_top.vhd
+++ b/hdl/top/golden/svec_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
-- Last update: 2014-01-31
+-- Last update: 2014-02-03
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -45,6 +45,7 @@ use IEEE.NUMERIC_STD.all;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
 use work.golden_core_pkg.all;
+use work.synthesis_descriptor.all;
 library UNISIM;
 use UNISIM.vcomponents.all;
@@ -177,12 +178,16 @@ architecture rtl of svec_top is
  constant c_MASTER_VME : integer := 0;
-  constant c_SLAVE_GOLDEN  : integer := 0;
+  constant c_SLAVE_GOLDEN   : integer := 0;
-  constant c_SLAVE_ONEWIRE : integer := 1;
+  constant c_SLAVE_ONEWIRE  : integer := 1;
+  constant c_DESC_SYNTHESIS : integer := 2;
+  constant c_DESC_REPO_URL  : integer := 3;
-  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
+  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 1 downto 0) :=
-    (c_SLAVE_GOLDEN  => f_sdb_embed_device(c_xwb_golden_sdb, x"00010000"),
+    (c_SLAVE_GOLDEN   => f_sdb_embed_device(c_xwb_golden_sdb, x"00010000"),
-     c_SLAVE_ONEWIRE => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00012000")
+     c_SLAVE_ONEWIRE  => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00012000"),
+     c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
+     c_DESC_REPO_URL  => f_sdb_embed_repo_url(c_sdb_repo_url)
     );
  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
@@ -338,7 +343,7 @@ begin
  trig0(24)           <= VME_DATA_DIR_int;
  trig0(25)           <= VME_addr_DIR_int;
  trig0(31 downto 26) <= VME_GA_i;
  trig1(30 downto 0) <= VME_ADDR_b;
  trig2(31 downto 0) <= VME_DATA_b;

--- a/hdl/top/golden/synthesis_descriptor.vhd
+++ b/hdl/top/golden/synthesis_descriptor.vhd
+-------------------------------------------------------------------------------
+-- Title      : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
+-- Project    : Fine Delay FMC (fmc-delay-1ns-4cha)
+-------------------------------------------------------------------------------
+-- File       : synthesis_descriptor.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2013-04-16
+-- Last update: 2013-04-16
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
+-- Contains synthesis & source repository information.
+-- Warning: this file is modified whenever a synthesis is executed.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use work.wishbone_pkg.all;
+package synthesis_descriptor is
+constant c_sdb_synthesis_info : t_sdb_synthesis :=
+  (
+    syn_module_name => "svec-golden     ",
+    syn_commit_id => "00000000000000000000000000000000",
+    syn_tool_name => "ISE     ",
+    syn_tool_version => x"00000133",
+    syn_date => x"20140203",
+    syn_username => "twlostow       ");
+constant c_sdb_repo_url : t_sdb_repo_url :=
+  (
+    repo_url => "git://ohwr.org/fmc-projects/svec.git                           " 
+  );
+end package synthesis_descriptor;
--- a/hdl/top/sfpga_bootloader/Manifest.py
+++ b/hdl/top/sfpga_bootloader/Manifest.py
@@ -4,5 +4,5 @@ fetchto = "../../ip_cores"
 modules = {
    "local" : ["../../rtl/bootloader" ],
-    "git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master" ]
+    "git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ]
    }