hdl: directory structure cleanup (moved template top levels to top/templates),…

hdl: directory structure cleanup (moved template top levels to top/templates), removed unused package dependency from svec_bootloader

hdl: directory structure cleanup (moved template top levels to top/templates),…
hdl: directory structure cleanup (moved template top levels to top/templates), removed unused package dependency from svec_bootloader
c07b9c17 · Tomasz Wlostowski · 45d4b96d · c07b9c17 · c07b9c17 · c07b9c17
Commit c07b9c17 authored Jun 20, 2012 by Tomasz Wlostowski
22 changed files
--- a/hdl/.gitignore
+++ b/hdl/.gitignore
 *~
 *#
 fifo_generator_v6_1
-testbench/svec_sfpga_top/sample_bitstream/
+testbench/sfpga_bootloader/sample_bitstream/
 *.*\#
 \#*
 .\#*

--- a/hdl/syn/svec_sfpga/Manifest.py
+++ b/hdl/syn/svec_sfpga/Manifest.py
@@ -9,4 +9,4 @@ syn_package = "ftg256"
 syn_top = "svec_sfpga_top"
 syn_project = "svec_sfpga.xise"
-modules = { "local" : [ "../../top/svec_sfpga", "../../platform" ] }
+modules = { "local" : [ "../../top/sfpga_bootloader", "../../platform" ] }
--- a/hdl/syn/sfpga_bootloader/svec_sfpga.xise
+++ b/hdl/syn/sfpga_bootloader/svec_sfpga.xise
--- a/hdl/syn/svec_sfpga/svec_sfpga.xise
+++ b/hdl/syn/svec_sfpga/svec_sfpga.xise
--- a/hdl/testbench/svec_sfpga_top/Manifest.py
+++ b/hdl/testbench/svec_sfpga_top/Manifest.py
@@ -5,5 +5,5 @@ vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/wb"
 files = [ "main.sv", "glbl.v", "SIM_CONFIG_S6_SERIAL.v" ]
-modules = { "local" :  [ "../../top/svec_sfpga" ] }
+modules = { "local" :  [ "../../top/sfpga_bootloader" ] }
--- a/hdl/testbench/svec_sfpga_top/SIM_CONFIG_S6_SERIAL.v
+++ b/hdl/testbench/svec_sfpga_top/SIM_CONFIG_S6_SERIAL.v
--- a/hdl/testbench/svec_sfpga_top/glbl.v
+++ b/hdl/testbench/svec_sfpga_top/glbl.v
--- a/hdl/testbench/svec_sfpga_top/main.sv
+++ b/hdl/testbench/svec_sfpga_top/main.sv
--- a/hdl/testbench/svec_sfpga_top/run.do
+++ b/hdl/testbench/svec_sfpga_top/run.do
--- a/hdl/testbench/svec_sfpga_top/sample_bitstream/crc_gen.bin
+++ b/hdl/testbench/svec_sfpga_top/sample_bitstream/crc_gen.bin
--- a/hdl/testbench/svec_sfpga_top/wave.do
+++ b/hdl/testbench/svec_sfpga_top/wave.do
--- a/hdl/top/svec_sfpga/Manifest.py
+++ b/hdl/top/svec_sfpga/Manifest.py
--- a/hdl/top/svec_sfpga/svec_sfpga_top.ucf
+++ b/hdl/top/svec_sfpga/svec_sfpga_top.ucf
--- a/hdl/top/svec_sfpga/svec_sfpga_top.vhd
+++ b/hdl/top/svec_sfpga/svec_sfpga_top.vhd
@@ -5,7 +5,6 @@ use IEEE.NUMERIC_STD.all;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
-use work.svl_wbgen2_pkg.all;
 library UNISIM;
 use UNISIM.vcomponents.all;

--- a/hdl/afpga/svec_v0_afpga.ucf
+++ b/hdl/afpga/svec_v0_afpga.ucf
--- a/hdl/afpga/svec_v0_afpga_top.vhd
+++ b/hdl/afpga/svec_v0_afpga_top.vhd
--- a/hdl/net2ucf/net2ucf_calay.py
+++ b/hdl/net2ucf/net2ucf_calay.py
--- a/hdl/net2ucf/svec_v0.net
+++ b/hdl/net2ucf/svec_v0.net
--- a/hdl/net2ucf/svec_v0_afpga.ucf.raw
+++ b/hdl/net2ucf/svec_v0_afpga.ucf.raw
--- a/hdl/net2ucf/svec_v0_sfpga.ucf.raw
+++ b/hdl/net2ucf/svec_v0_sfpga.ucf.raw
--- a/hdl/sfpga/svec_v0_sfpga.ucf
+++ b/hdl/sfpga/svec_v0_sfpga.ucf
--- a/hdl/sfpga/svec_v0_sfpga_top.vhd
+++ b/hdl/sfpga/svec_v0_sfpga_top.vhd