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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
c0609a33
Commit
c0609a33
authored
Jun 21, 2012
by
Tomasz Wlostowski
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software/sveclib: updated Xloader register map
parent
f268d401
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xloader_regs.h
software/sveclib/xloader_regs.h
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software/sveclib/xloader_regs.h
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c0609a33
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@@ -3,7 +3,7 @@
* File : xloader_regs.h
* Author : auto-generated by wbgen2 from xloader_wb.wb
* Created : T
ue Jun 19 16:25:33
2012
* Created : T
hu Jun 21 15:17:30
2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xloader_wb.wb
...
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@@ -64,6 +64,8 @@
/* definitions for register: GPIO Output Register */
/* definitions for register: ID Register */
/* definitions for register: FIFO 'Bitstream FIFO' data input register 0 */
/* definitions for field: Entry size in reg: FIFO 'Bitstream FIFO' data input register 0 */
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@@ -91,6 +93,9 @@
/* definitions for field: FIFO empty flag in reg: FIFO 'Bitstream FIFO' control/status register */
#define XLDR_FIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO clear in reg: FIFO 'Bitstream FIFO' control/status register */
#define XLDR_FIFO_CSR_CLEAR_BUS WBGEN2_GEN_MASK(18, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Bitstream FIFO' control/status register */
#define XLDR_FIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define XLDR_FIFO_CSR_USEDW_SHIFT 0
...
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@@ -102,10 +107,12 @@
#define XLDR_REG_BTRIGR 0x00000004
/* [0x8]: REG GPIO Output Register */
#define XLDR_REG_GPIOR 0x00000008
/* [0xc]: REG FIFO 'Bitstream FIFO' data input register 0 */
#define XLDR_REG_FIFO_R0 0x0000000c
/* [0x10]: REG FIFO 'Bitstream FIFO' data input register 1 */
#define XLDR_REG_FIFO_R1 0x00000010
/* [0x14]: REG FIFO 'Bitstream FIFO' control/status register */
#define XLDR_REG_FIFO_CSR 0x00000014
/* [0xc]: REG ID Register */
#define XLDR_REG_IDR 0x0000000c
/* [0x10]: REG FIFO 'Bitstream FIFO' data input register 0 */
#define XLDR_REG_FIFO_R0 0x00000010
/* [0x14]: REG FIFO 'Bitstream FIFO' data input register 1 */
#define XLDR_REG_FIFO_R1 0x00000014
/* [0x18]: REG FIFO 'Bitstream FIFO' control/status register */
#define XLDR_REG_FIFO_CSR 0x00000018
#endif
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