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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
9ab7e2c6
Commit
9ab7e2c6
authored
Feb 08, 2021
by
Tristan Gingold
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vme16_test: use pipelined wb, fix memmap comment
parent
a3227e11
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6 deletions
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-6
svec_vme16.vhd
hdl/top/vme16_test/svec_vme16.vhd
+2
-1
vmecore_test.vhd
hdl/top/vme16_test/vmecore_test.vhd
+5
-5
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hdl/top/vme16_test/svec_vme16.vhd
View file @
9ab7e2c6
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 20
17-1
2-05
-- Last update: 20
21-0
2-05
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
...
...
@@ -218,6 +218,7 @@ begin -- architecture top
g_ENABLE_CR_CSR
=>
False
,
g_USER_CSR_EXT
=>
False
,
g_WB_GRANULARITY
=>
BYTE
,
g_WB_MODE
=>
PIPELINED
,
g_MANUFACTURER_ID
=>
c_CERN_ID
,
g_BOARD_ID
=>
c_SVEC_ID
,
...
...
hdl/top/vme16_test/vmecore_test.vhd
View file @
9ab7e2c6
...
...
@@ -52,11 +52,11 @@ architecture rtl of vmecore_test is
-- Memory map:
-- 0x000 - 0x3ff: sram (512*2B)
-- 0x400: leds (4B)
-- 0x40
1
: last WB transaction (see the code for the format)
-- 0x40
2
: nbr of WB read accesses (write to clear)
-- 0x40
3
: nbr of WB write accesses (likewise)
-- 0x40
4
: nbr of write errors in pattern ram
-- 0x40
5
: generates bus error.
-- 0x40
2
: last WB transaction (see the code for the format)
-- 0x40
4
: nbr of WB read accesses (write to clear)
-- 0x40
6
: nbr of WB write accesses (likewise)
-- 0x40
8
: nbr of write errors in pattern ram
-- 0x40
a
: generates bus error.
-- 0x800: counter (2B). Generate an interrupt when 0 is reached.
-- 0xc00: pattern ram (0x1000 * 4B)
signal
counter
:
unsigned
(
15
downto
0
);
...
...
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