Commit 9ab7e2c6 authored by Tristan Gingold's avatar Tristan Gingold

vme16_test: use pipelined wb, fix memmap comment

parent a3227e11
......@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2017-12-05
-- Last update: 2021-02-05
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
......@@ -218,6 +218,7 @@ begin -- architecture top
g_ENABLE_CR_CSR => False,
g_USER_CSR_EXT => False,
g_WB_GRANULARITY => BYTE,
g_WB_MODE => PIPELINED,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
......
......@@ -52,11 +52,11 @@ architecture rtl of vmecore_test is
-- Memory map:
-- 0x000 - 0x3ff: sram (512*2B)
-- 0x400: leds (4B)
-- 0x401: last WB transaction (see the code for the format)
-- 0x402: nbr of WB read accesses (write to clear)
-- 0x403: nbr of WB write accesses (likewise)
-- 0x404: nbr of write errors in pattern ram
-- 0x405: generates bus error.
-- 0x402: last WB transaction (see the code for the format)
-- 0x404: nbr of WB read accesses (write to clear)
-- 0x406: nbr of WB write accesses (likewise)
-- 0x408: nbr of write errors in pattern ram
-- 0x40a: generates bus error.
-- 0x800: counter (2B). Generate an interrupt when 0 is reached.
-- 0xc00: pattern ram (0x1000 * 4B)
signal counter : unsigned(15 downto 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment