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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
93d8e6b1
Commit
93d8e6b1
authored
Apr 06, 2020
by
Tristan Gingold
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vmecore_test: cleanup and update.
parent
a600f8c8
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3 changed files
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6 additions
and
14 deletions
+6
-14
Manifest.py
hdl/top/vmecore_test/Manifest.py
+2
-2
svec_vmecore_test_top.vhd
hdl/top/vmecore_test/svec_vmecore_test_top.vhd
+2
-11
vmecore_test.vhd
hdl/top/vmecore_test/vmecore_test.vhd
+2
-1
No files found.
hdl/top/vmecore_test/Manifest.py
View file @
93d8e6b1
...
...
@@ -4,6 +4,6 @@ files = [
"vmecore_test.vhd"
,
]
modules
=
{
"local"
:
[
"../../ip_cores/general-cores
"
,
"../../ip_cores/vme64x-core
"
]
modules
=
{
'git'
:
[
"git://ohwr.org/project/general-cores.git
"
,
"git://ohwr.org/project/vme64x-core.git
"
]
}
hdl/top/vmecore_test/svec_vmecore_test_top.vhd
View file @
93d8e6b1
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 20
17-12-05
-- Last update: 20
20-03-12
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
...
...
@@ -176,13 +176,6 @@ architecture top of svec_vmecore_test_top is
signal
master_out
:
t_wishbone_master_out
;
signal
master_in
:
t_wishbone_master_in
;
-- clock and reset
signal
clk_sys_62m5
:
std_logic
;
signal
rst_sys_62m5_n
:
std_logic
;
signal
clk_ref_125m
:
std_logic
;
signal
clk_ref_div2
:
std_logic
;
signal
clk_ext_ref
:
std_logic
;
-- VME
signal
vme_data_b_out
:
std_logic_vector
(
31
downto
0
);
signal
vme_addr_b_out
:
std_logic_vector
(
31
downto
1
);
...
...
@@ -194,9 +187,6 @@ architecture top of svec_vmecore_test_top is
signal
vme_irq_n_o
:
std_logic_vector
(
7
downto
1
);
-- LEDs and GPIO
signal
pps
:
std_logic
;
signal
pps_led
:
std_logic
;
signal
pps_ext_in
:
std_logic
;
signal
svec_led
:
std_logic_vector
(
15
downto
0
);
signal
pllout_clk_fb_sys
,
pllout_clk_sys
:
std_logic
;
...
...
@@ -297,6 +287,7 @@ begin -- architecture top
g_CLOCK_PERIOD
=>
8
,
g_DECODE_AM
=>
True
,
g_USER_CSR_EXT
=>
False
,
g_wb_granularity
=>
WORD
,
g_MANUFACTURER_ID
=>
c_CERN_ID
,
g_BOARD_ID
=>
c_SVEC_ID
,
...
...
hdl/top/vmecore_test/vmecore_test.vhd
View file @
93d8e6b1
...
...
@@ -42,6 +42,7 @@ entity vmecore_test is
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
int_o
:
out
std_logic
;
leds_o
:
out
std_logic_vector
(
15
downto
0
));
end
vmecore_test
;
...
...
@@ -219,7 +220,7 @@ begin
end
process
;
leds_o
<=
leds
;
slave_o
.
int
<=
'1'
when
counter
=
1
else
'0'
;
int_o
<=
'1'
when
counter
=
1
else
'0'
;
-- drive unused WB slave_o outputs
slave_o
.
stall
<=
'0'
;
...
...
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