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Simple VME FMC Carrier SVEC
Commit 92bd66ca authored by Matthieu Cattin's avatar Matthieu Cattin
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Updating ddr test with bicolor led controller and ucf for pcb v1.

parent 13e85c71
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Showing with 209 additions and 161 deletions
hdl/top/ddr_test/Manifest.py
View file @ 92bd66ca
files = [ "svec_afpga_top.vhd", files = [ "svec_afpga_top.vhd",
"svec_v0_afpga.ucf", "svec_v1_afpga.ucf",
"csr.vhd", "csr.vhd",
"wb_addr_decoder.vhd"] "wb_addr_decoder.vhd",
"../bicolor_led_test/bicolor_led_ctrl.vhd",
"../bicolor_led_test/bicolor_led_ctrl_pkg.vhd"]
""" """
fetchto = "ip_cores" fetchto = "ip_cores"
......
hdl/top/ddr_test/csr.htm
View file @ 92bd66ca
...@@ -515,10 +515,10 @@ csr_stat_reserved_i[22:0] ...@@ -515,10 +515,10 @@ csr_stat_reserved_i[22:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
csr_ctrl_fp_leds_o[7:0] csr_ctrl_fp_leds_auto_o
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rArr; &rarr;
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -532,7 +532,7 @@ csr_ctrl_fp_leds_o[7:0] ...@@ -532,7 +532,7 @@ csr_ctrl_fp_leds_o[7:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
csr_ctrl_dbg_leds_o[3:0] csr_ctrl_fp_leds_o[15:0]
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rArr; &rArr;
...@@ -549,7 +549,7 @@ csr_ctrl_dbg_leds_o[3:0] ...@@ -549,7 +549,7 @@ csr_ctrl_dbg_leds_o[3:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
csr_ctrl_gpio_term_o[3:0] csr_ctrl_fp_led_int_o[6:0]
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rArr; &rArr;
...@@ -623,23 +623,6 @@ csr_ctrl_gpio_out_o[3:0] ...@@ -623,23 +623,6 @@ csr_ctrl_gpio_out_o[3:0]
&rArr; &rArr;
</td> </td>
</tr> </tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
csr_ctrl_reserved_o[8:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table> </table>
<h3><a name="sect_3_0">3. Register description</a></h3> <h3><a name="sect_3_0">3. Register description</a></h3>
...@@ -1771,20 +1754,20 @@ CTRL ...@@ -1771,20 +1754,20 @@ CTRL
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[8:1] -
</td> </td>
<td > <td style="border: solid 1px black;" colspan=4 class="td_field">
GPIO_OUT[3:0]
</td> </td>
<td > <td style="border: solid 1px black;" colspan=1 class="td_field">
GPIO_34_DIR
</td> </td>
<td > <td style="border: solid 1px black;" colspan=1 class="td_field">
GPIO_2_DIR
</td> </td>
<td > <td style="border: solid 1px black;" colspan=1 class="td_field">
GPIO_1_DIR
</td> </td>
<td > <td >
...@@ -1825,20 +1808,20 @@ RESERVED[8:1] ...@@ -1825,20 +1808,20 @@ RESERVED[8:1]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[0:0] FP_LED_INT[6:0]
</td>
<td style="border: solid 1px black;" colspan=4 class="td_field">
GPIO_OUT[3:0]
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
GPIO_34_DIR FP_LEDS[15:15]
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td >
GPIO_2_DIR
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td >
GPIO_1_DIR
</td>
<td >
</td> </td>
<td > <td >
...@@ -1879,11 +1862,11 @@ GPIO_1_DIR ...@@ -1879,11 +1862,11 @@ GPIO_1_DIR
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=4 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
GPIO_TERM[3:0] FP_LEDS[14:7]
</td> </td>
<td style="border: solid 1px black;" colspan=4 class="td_field"> <td >
DBG_LEDS[3:0]
</td> </td>
<td > <td >
...@@ -1933,11 +1916,11 @@ DBG_LEDS[3:0] ...@@ -1933,11 +1916,11 @@ DBG_LEDS[3:0]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=7 class="td_field">
FP_LEDS[7:0] FP_LEDS[6:0]
</td> </td>
<td > <td style="border: solid 1px black;" colspan=1 class="td_field">
FP_LEDS_AUTO
</td> </td>
<td > <td >
...@@ -1961,17 +1944,17 @@ FP_LEDS[7:0] ...@@ -1961,17 +1944,17 @@ FP_LEDS[7:0]
</table> </table>
<ul> <ul>
<li><b> <li><b>
FP_LEDS_AUTO
</b>[<i>read/write</i>]: Automatic front panel LEDs
<br>Automatic front panel LEDs control
<li><b>
FP_LEDS FP_LEDS
</b>[<i>read/write</i>]: Front panel LEDs </b>[<i>read/write</i>]: Front panel LEDs
<br>Front panel LEDs control <br>Front panel LEDs control
<li><b> <li><b>
DBG_LEDS FP_LED_INT
</b>[<i>read/write</i>]: Debug LEDs </b>[<i>read/write</i>]: Front panel LED intensity
<br>On board debug LEDs control <br>Front panel LED intensity in %
<li><b>
GPIO_TERM
</b>[<i>read/write</i>]: GPIO termination
<br>GPIO termination enable.<br>0 = disabled<br>1 = enabled
<li><b> <li><b>
GPIO_1_DIR GPIO_1_DIR
</b>[<i>read/write</i>]: GPIO 1 direction </b>[<i>read/write</i>]: GPIO 1 direction
...@@ -1988,10 +1971,6 @@ GPIO_34_DIR ...@@ -1988,10 +1971,6 @@ GPIO_34_DIR
GPIO_OUT GPIO_OUT
</b>[<i>read/write</i>]: GPIO outputs </b>[<i>read/write</i>]: GPIO outputs
<br>GPIO ouputs value <br>GPIO ouputs value
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul> </ul>
......
hdl/top/ddr_test/csr.vhd
View file @ 92bd66ca
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : csr.vhd -- File : csr.vhd
-- Author : auto-generated by wbgen2 from csr.wb -- Author : auto-generated by wbgen2 from csr.wb
-- Created : Tue Sep 4 16:47:37 2012 -- Created : Thu Oct 25 18:23:00 2012
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE csr.wb
...@@ -50,12 +50,12 @@ entity csr is ...@@ -50,12 +50,12 @@ entity csr is
csr_stat_gpio_in_i : in std_logic_vector(3 downto 0); csr_stat_gpio_in_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status' -- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
csr_stat_reserved_i : in std_logic_vector(22 downto 0); csr_stat_reserved_i : in std_logic_vector(22 downto 0);
-- Port for BIT field: 'Automatic front panel LEDs' in reg: 'Control'
csr_ctrl_fp_leds_auto_o : out std_logic;
-- Port for std_logic_vector field: 'Front panel LEDs' in reg: 'Control' -- Port for std_logic_vector field: 'Front panel LEDs' in reg: 'Control'
csr_ctrl_fp_leds_o : out std_logic_vector(7 downto 0); csr_ctrl_fp_leds_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Debug LEDs' in reg: 'Control' -- Port for std_logic_vector field: 'Front panel LED intensity' in reg: 'Control'
csr_ctrl_dbg_leds_o : out std_logic_vector(3 downto 0); csr_ctrl_fp_led_int_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'GPIO termination' in reg: 'Control'
csr_ctrl_gpio_term_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'GPIO 1 direction' in reg: 'Control' -- Port for BIT field: 'GPIO 1 direction' in reg: 'Control'
csr_ctrl_gpio_1_dir_o : out std_logic; csr_ctrl_gpio_1_dir_o : out std_logic;
-- Port for BIT field: 'GPIO 2 direction' in reg: 'Control' -- Port for BIT field: 'GPIO 2 direction' in reg: 'Control'
...@@ -63,22 +63,19 @@ entity csr is ...@@ -63,22 +63,19 @@ entity csr is
-- Port for BIT field: 'GPIO 3 and 4 direction' in reg: 'Control' -- Port for BIT field: 'GPIO 3 and 4 direction' in reg: 'Control'
csr_ctrl_gpio_34_dir_o : out std_logic; csr_ctrl_gpio_34_dir_o : out std_logic;
-- Port for std_logic_vector field: 'GPIO outputs' in reg: 'Control' -- Port for std_logic_vector field: 'GPIO outputs' in reg: 'Control'
csr_ctrl_gpio_out_o : out std_logic_vector(3 downto 0); csr_ctrl_gpio_out_o : out std_logic_vector(3 downto 0)
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
csr_ctrl_reserved_o : out std_logic_vector(8 downto 0)
); );
end csr; end csr;
architecture syn of csr is architecture syn of csr is
signal csr_ctrl_fp_leds_int : std_logic_vector(7 downto 0); signal csr_ctrl_fp_leds_auto_int : std_logic ;
signal csr_ctrl_dbg_leds_int : std_logic_vector(3 downto 0); signal csr_ctrl_fp_leds_int : std_logic_vector(15 downto 0);
signal csr_ctrl_gpio_term_int : std_logic_vector(3 downto 0); signal csr_ctrl_fp_led_int_int : std_logic_vector(6 downto 0);
signal csr_ctrl_gpio_1_dir_int : std_logic ; signal csr_ctrl_gpio_1_dir_int : std_logic ;
signal csr_ctrl_gpio_2_dir_int : std_logic ; signal csr_ctrl_gpio_2_dir_int : std_logic ;
signal csr_ctrl_gpio_34_dir_int : std_logic ; signal csr_ctrl_gpio_34_dir_int : std_logic ;
signal csr_ctrl_gpio_out_int : std_logic_vector(3 downto 0); signal csr_ctrl_gpio_out_int : std_logic_vector(3 downto 0);
signal csr_ctrl_reserved_int : std_logic_vector(8 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
...@@ -108,14 +105,13 @@ begin ...@@ -108,14 +105,13 @@ begin
ack_sreg <= "0000000000"; ack_sreg <= "0000000000";
ack_in_progress <= '0'; ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
csr_ctrl_fp_leds_int <= "00000000"; csr_ctrl_fp_leds_auto_int <= '0';
csr_ctrl_dbg_leds_int <= "0000"; csr_ctrl_fp_leds_int <= "0000000000000000";
csr_ctrl_gpio_term_int <= "0000"; csr_ctrl_fp_led_int_int <= "0000000";
csr_ctrl_gpio_1_dir_int <= '0'; csr_ctrl_gpio_1_dir_int <= '0';
csr_ctrl_gpio_2_dir_int <= '0'; csr_ctrl_gpio_2_dir_int <= '0';
csr_ctrl_gpio_34_dir_int <= '0'; csr_ctrl_gpio_34_dir_int <= '0';
csr_ctrl_gpio_out_int <= "0000"; csr_ctrl_gpio_out_int <= "0000";
csr_ctrl_reserved_int <= "000000000";
elsif rising_edge(bus_clock_int) then elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
...@@ -171,26 +167,26 @@ begin ...@@ -171,26 +167,26 @@ begin
ack_in_progress <= '1'; ack_in_progress <= '1';
when "100" => when "100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
csr_ctrl_fp_leds_int <= wrdata_reg(7 downto 0); rddata_reg(0) <= 'X';
csr_ctrl_dbg_leds_int <= wrdata_reg(11 downto 8); csr_ctrl_fp_leds_auto_int <= wrdata_reg(0);
csr_ctrl_gpio_term_int <= wrdata_reg(15 downto 12); csr_ctrl_fp_leds_int <= wrdata_reg(16 downto 1);
rddata_reg(16) <= 'X'; csr_ctrl_fp_led_int_int <= wrdata_reg(23 downto 17);
csr_ctrl_gpio_1_dir_int <= wrdata_reg(16); rddata_reg(24) <= 'X';
rddata_reg(17) <= 'X'; csr_ctrl_gpio_1_dir_int <= wrdata_reg(24);
csr_ctrl_gpio_2_dir_int <= wrdata_reg(17); rddata_reg(25) <= 'X';
rddata_reg(18) <= 'X'; csr_ctrl_gpio_2_dir_int <= wrdata_reg(25);
csr_ctrl_gpio_34_dir_int <= wrdata_reg(18); rddata_reg(26) <= 'X';
csr_ctrl_gpio_out_int <= wrdata_reg(22 downto 19); csr_ctrl_gpio_34_dir_int <= wrdata_reg(26);
csr_ctrl_reserved_int <= wrdata_reg(31 downto 23); csr_ctrl_gpio_out_int <= wrdata_reg(30 downto 27);
else else
rddata_reg(7 downto 0) <= csr_ctrl_fp_leds_int; rddata_reg(0) <= csr_ctrl_fp_leds_auto_int;
rddata_reg(11 downto 8) <= csr_ctrl_dbg_leds_int; rddata_reg(16 downto 1) <= csr_ctrl_fp_leds_int;
rddata_reg(15 downto 12) <= csr_ctrl_gpio_term_int; rddata_reg(23 downto 17) <= csr_ctrl_fp_led_int_int;
rddata_reg(16) <= csr_ctrl_gpio_1_dir_int; rddata_reg(24) <= csr_ctrl_gpio_1_dir_int;
rddata_reg(17) <= csr_ctrl_gpio_2_dir_int; rddata_reg(25) <= csr_ctrl_gpio_2_dir_int;
rddata_reg(18) <= csr_ctrl_gpio_34_dir_int; rddata_reg(26) <= csr_ctrl_gpio_34_dir_int;
rddata_reg(22 downto 19) <= csr_ctrl_gpio_out_int; rddata_reg(30 downto 27) <= csr_ctrl_gpio_out_int;
rddata_reg(31 downto 23) <= csr_ctrl_reserved_int; rddata_reg(31) <= 'X';
end if; end if;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
...@@ -219,12 +215,12 @@ begin ...@@ -219,12 +215,12 @@ begin
-- DDR3 bank5 calibration status -- DDR3 bank5 calibration status
-- GPIO inputs -- GPIO inputs
-- Reserved -- Reserved
-- Automatic front panel LEDs
csr_ctrl_fp_leds_auto_o <= csr_ctrl_fp_leds_auto_int;
-- Front panel LEDs -- Front panel LEDs
csr_ctrl_fp_leds_o <= csr_ctrl_fp_leds_int; csr_ctrl_fp_leds_o <= csr_ctrl_fp_leds_int;
-- Debug LEDs -- Front panel LED intensity
csr_ctrl_dbg_leds_o <= csr_ctrl_dbg_leds_int; csr_ctrl_fp_led_int_o <= csr_ctrl_fp_led_int_int;
-- GPIO termination
csr_ctrl_gpio_term_o <= csr_ctrl_gpio_term_int;
-- GPIO 1 direction -- GPIO 1 direction
csr_ctrl_gpio_1_dir_o <= csr_ctrl_gpio_1_dir_int; csr_ctrl_gpio_1_dir_o <= csr_ctrl_gpio_1_dir_int;
-- GPIO 2 direction -- GPIO 2 direction
...@@ -233,8 +229,6 @@ begin ...@@ -233,8 +229,6 @@ begin
csr_ctrl_gpio_34_dir_o <= csr_ctrl_gpio_34_dir_int; csr_ctrl_gpio_34_dir_o <= csr_ctrl_gpio_34_dir_int;
-- GPIO outputs -- GPIO outputs
csr_ctrl_gpio_out_o <= csr_ctrl_gpio_out_int; csr_ctrl_gpio_out_o <= csr_ctrl_gpio_out_int;
-- Reserved
csr_ctrl_reserved_o <= csr_ctrl_reserved_int;
rwaddr_reg <= wb_addr_i; rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0); wb_ack_o <= ack_sreg(0);
......
hdl/top/ddr_test/csr.wb
View file @ 92bd66ca
...@@ -143,31 +143,30 @@ peripheral { ...@@ -143,31 +143,30 @@ peripheral {
prefix = "ctrl"; prefix = "ctrl";
field { field {
name = "Front panel LEDs"; name = "Automatic front panel LEDs";
description = "Front panel LEDs control"; description = "Automatic front panel LEDs control";
prefix = "fp_leds"; prefix = "fp_leds_auto";
type = SLV; type = BIT;
size = 8;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "Debug LEDs"; name = "Front panel LEDs";
description = "On board debug LEDs control"; description = "Front panel LEDs control";
prefix = "dbg_leds"; prefix = "fp_leds";
type = SLV; type = SLV;
size = 4; size = 16;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "GPIO termination"; name = "Front panel LED intensity";
description = "GPIO termination enable.\n0 = disabled\n1 = enabled"; description = "Front panel LED intensity in %";
prefix = "gpio_term"; prefix = "fp_led_int";
type = SLV; type = SLV;
size = 4; size = 7;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -209,15 +208,6 @@ peripheral { ...@@ -209,15 +208,6 @@ peripheral {
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 9;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
}; };
}; };
hdl/top/ddr_test/svec_afpga_top.vhd
View file @ 92bd66ca
...@@ -47,6 +47,8 @@ use work.ddr3_ctrl_pkg.all; ...@@ -47,6 +47,8 @@ use work.ddr3_ctrl_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.vme64x_pack.all; use work.vme64x_pack.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.bicolor_led_ctrl_pkg.all;
entity svec_afpga_top is entity svec_afpga_top is
generic( generic(
...@@ -312,7 +314,9 @@ entity svec_afpga_top is ...@@ -312,7 +314,9 @@ entity svec_afpga_top is
term_en_o : out std_logic_vector(4 downto 1); term_en_o : out std_logic_vector(4 downto 1);
fp_led_n_o : out std_logic_vector(7 downto 0); fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0);
------------------------------------------ ------------------------------------------
-- 1-wire thermoeter + unique ID -- 1-wire thermoeter + unique ID
...@@ -449,14 +453,13 @@ architecture rtl of svec_afpga_top is ...@@ -449,14 +453,13 @@ architecture rtl of svec_afpga_top is
csr_stat_ddr3_bank5_cal_done_i : in std_logic; csr_stat_ddr3_bank5_cal_done_i : in std_logic;
csr_stat_gpio_in_i : in std_logic_vector(3 downto 0); csr_stat_gpio_in_i : in std_logic_vector(3 downto 0);
csr_stat_reserved_i : in std_logic_vector(22 downto 0); csr_stat_reserved_i : in std_logic_vector(22 downto 0);
csr_ctrl_fp_leds_o : out std_logic_vector(7 downto 0); csr_ctrl_fp_leds_auto_o : out std_logic;
csr_ctrl_dbg_leds_o : out std_logic_vector(3 downto 0); csr_ctrl_fp_leds_o : out std_logic_vector(15 downto 0);
csr_ctrl_gpio_term_o : out std_logic_vector(3 downto 0); csr_ctrl_fp_led_int_o : out std_logic_vector(6 downto 0);
csr_ctrl_gpio_1_dir_o : out std_logic; csr_ctrl_gpio_1_dir_o : out std_logic;
csr_ctrl_gpio_2_dir_o : out std_logic; csr_ctrl_gpio_2_dir_o : out std_logic;
csr_ctrl_gpio_34_dir_o : out std_logic; csr_ctrl_gpio_34_dir_o : out std_logic;
csr_ctrl_gpio_out_o : out std_logic_vector(3 downto 0); csr_ctrl_gpio_out_o : out std_logic_vector(3 downto 0)
csr_ctrl_reserved_o : out std_logic_vector(8 downto 0)
); );
end component csr; end component csr;
...@@ -554,10 +557,20 @@ architecture rtl of svec_afpga_top is ...@@ -554,10 +557,20 @@ architecture rtl of svec_afpga_top is
signal owr_en : std_logic_vector(c_ONEWIRE_NB - 1 downto 0); signal owr_en : std_logic_vector(c_ONEWIRE_NB - 1 downto 0);
signal owr_i : std_logic_vector(c_ONEWIRE_NB - 1 downto 0); signal owr_i : std_logic_vector(c_ONEWIRE_NB - 1 downto 0);
-- LEDs -- Front panel LEDs
signal led_blink_cnt : unsigned(25 downto 0); signal led_blink_cnt : unsigned(25 downto 0);
signal led_blink : std_logic; signal led_blink : std_logic;
signal fp_led_n : std_logic_vector(7 downto 0); signal led_blink_d : std_logic;
signal led_blink_p : std_logic;
signal led_intensity : std_logic_vector(6 downto 0);
signal led_state_auto : std_logic_vector(15 downto 0);
signal led_state : std_logic_vector(15 downto 0);
signal led_auto : std_logic;
signal led_state_man : std_logic_vector(15 downto 0);
signal led_state_seq : unsigned(3 downto 0);
signal led_column : std_logic_vector(3 downto 0);
signal led_line : std_logic_vector(1 downto 0);
signal led_line_oen : std_logic_vector(1 downto 0);
-- DDR access FIFOs -- DDR access FIFOs
signal ddr_bank4_addr_cnt : unsigned(31 downto 0); signal ddr_bank4_addr_cnt : unsigned(31 downto 0);
...@@ -805,14 +818,13 @@ begin ...@@ -805,14 +818,13 @@ begin
csr_stat_ddr3_bank5_cal_done_i => ddr3_bank5_status(0), csr_stat_ddr3_bank5_cal_done_i => ddr3_bank5_status(0),
csr_stat_gpio_in_i => gpio_in, csr_stat_gpio_in_i => gpio_in,
csr_stat_reserved_i => "00000000000000000000000", csr_stat_reserved_i => "00000000000000000000000",
csr_ctrl_fp_leds_o => fp_led_n, csr_ctrl_fp_leds_auto_o => led_auto,
csr_ctrl_dbg_leds_o => dbg_led_n_o, csr_ctrl_fp_leds_o => led_state_man,
csr_ctrl_gpio_term_o => term_en_o, csr_ctrl_fp_led_int_o => led_intensity,
csr_ctrl_gpio_1_dir_o => gpio_1_dir, csr_ctrl_gpio_1_dir_o => gpio_1_dir,
csr_ctrl_gpio_2_dir_o => gpio_2_dir, csr_ctrl_gpio_2_dir_o => gpio_2_dir,
csr_ctrl_gpio_34_dir_o => gpio_34_dir, csr_ctrl_gpio_34_dir_o => gpio_34_dir,
csr_ctrl_gpio_out_o => gpio_out, csr_ctrl_gpio_out_o => gpio_out
csr_ctrl_reserved_o => open
); );
wb_stall(c_WB_CSR) <= '0'; wb_stall(c_WB_CSR) <= '0';
...@@ -1163,8 +1175,11 @@ begin ...@@ -1163,8 +1175,11 @@ begin
gpio_in <= fp_gpio_b; gpio_in <= fp_gpio_b;
term_en_o <= (others => '0');
dbg_led_n_o <= (others => '0');
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- LEDs -- Front-panel LEDs
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
process (sys_clk) process (sys_clk)
begin begin
...@@ -1175,12 +1190,80 @@ begin ...@@ -1175,12 +1190,80 @@ begin
else else
led_blink <= '0'; led_blink <= '0';
end if; end if;
led_blink_d <= led_blink;
end if;
end process;
led_blink_p <= led_blink and not(led_blink_d);
process (sys_clk)
begin
if rising_edge(sys_clk) then
if sys_rst_n = '0' then
led_state_seq <= (others => '0');
elsif led_blink_p = '1' then
led_state_seq <= led_state_seq + 1;
end if;
end if; end if;
end process; end process;
l_fp_led : for I in 0 to 7 generate
fp_led_n_o(I) <= not(fp_led_n(I) or led_blink); -- led_state bits : 15 0
end generate l_fp_led; -- ---------------------------------
-- fp led number : | 5 | 6 | 7 | 8 | 1 | 2 | 3 | 4 |
--
-- 2 bits per LED
-- 00 => OFF
-- 01 => Green
-- 10 => Red
-- 11 => Orange
led_state_auto <= X"00AA" when led_state_seq = "0000" else -- 1,2,3,4 = red | 5,6,7,8 = off
X"AA00" when led_state_seq = "0001" else -- 1,2,3,4 = off | 5,6,7,8 = red
X"4040" when led_state_seq = "0010" else -- 1,5 = green | 2,3,4,6,7,8 = off
X"1010" when led_state_seq = "0011" else -- 2,6 = green | 1,3,4,5,7,8 = off
X"0404" when led_state_seq = "0100" else -- 3,7 = green | 1,2,4,5,6,8 = off
X"0101" when led_state_seq = "0101" else -- 4,8 = green | 1,2,3,5,6,7 = off
X"00C0" when led_state_seq = "0110" else -- 1 = orange | 2,3,4,5,6,7,8 = off
X"0030" when led_state_seq = "0111" else -- 2 = orange | 1,3,4,5,6,7,8 = off
X"000C" when led_state_seq = "1000" else -- 3 = orange | 1,2,4,5,6,7,8 = off
X"0003" when led_state_seq = "1001" else -- 4 = orange | 1,2,3,5,6,7,8 = off
X"0300" when led_state_seq = "1010" else -- 8 = orange | 1,2,3,4,5,6,7 = off
X"0C00" when led_state_seq = "1011" else -- 7 = orange | 1,2,3,4,5,6,8 = off
X"3000" when led_state_seq = "1100" else -- 6 = orange | 1,2,3,4,5,7,8 = off
X"C000" when led_state_seq = "1101" else -- 5 = orange | 1,2,3,4,6,7,8 = off
X"0000" when led_state_seq = "1110" else -- all off
X"0000" when led_state_seq = "1111" else -- all off
X"0000";
--led_intensity <= std_logic_vector(to_unsigned(100, led_intensity'length)); -- 100% intensity
led_state <= led_state_auto when led_auto = '1' else led_state_man;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map(
g_NB_COLUMN => 4,
g_NB_LINE => 2,
g_CLK_FREQ => 62500000, -- in Hz
g_REFRESH_RATE => 250 -- in Hz
)
port map(
rst_n_i => sys_rst_n,
clk_i => sys_clk,
led_intensity_i => led_intensity, -- in %
led_state_i => led_state,
column_o => led_column,
line_o => led_line,
line_oen_o => led_line_oen
);
fp_led_column_o <= led_column;-- when led_auto = '1' else led_state_man(3 downto 0);
fp_led_line_o <= led_line;-- when led_auto = '1' else led_state_man(5 downto 4);
fp_led_line_oen_o <= led_line_oen;-- when led_auto = '1' else led_state_man(7 downto 6);
end rtl; end rtl;
hdl/top/ddr_test/svec_v1_afpga.ucf
View file @ 92bd66ca
...@@ -600,14 +600,14 @@ NET "term_en_o[2]" LOC = W5; ...@@ -600,14 +600,14 @@ NET "term_en_o[2]" LOC = W5;
NET "term_en_o[3]" LOC = W4; NET "term_en_o[3]" LOC = W4;
NET "term_en_o[4]" LOC = V4; NET "term_en_o[4]" LOC = V4;
NET "fp_led_n_o[0]" LOC = AD27; NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_n_o[1]" LOC = AD26; NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_n_o[2]" LOC = AC28; NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_n_o[3]" LOC = AC27; NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_n_o[4]" LOC = AE27; NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_n_o[5]" LOC = AE30; NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_n_o[6]" LOC = AF28; NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_n_o[7]" LOC = AE28; NET "fp_led_column_o[3]" LOC = AF28;
#---------------------------------------- #----------------------------------------
# 1-wire thermoeter + unique ID # 1-wire thermoeter + unique ID
...@@ -1201,14 +1201,14 @@ NET "term_en_o[2]" IOSTANDARD = "LVCMOS33"; ...@@ -1201,14 +1201,14 @@ NET "term_en_o[2]" IOSTANDARD = "LVCMOS33";
NET "term_en_o[3]" IOSTANDARD = "LVCMOS33"; NET "term_en_o[3]" IOSTANDARD = "LVCMOS33";
NET "term_en_o[4]" IOSTANDARD = "LVCMOS33"; NET "term_en_o[4]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[0]" IOSTANDARD = "LVCMOS33"; NET "fp_led_line_oen_o[0]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[1]" IOSTANDARD = "LVCMOS33"; NET "fp_led_line_oen_o[1]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[2]" IOSTANDARD = "LVCMOS33"; NET "fp_led_line_o[0]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[3]" IOSTANDARD = "LVCMOS33"; NET "fp_led_line_o[1]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[4]" IOSTANDARD = "LVCMOS33"; NET "fp_led_column_o[0]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[5]" IOSTANDARD = "LVCMOS33"; NET "fp_led_column_o[1]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[6]" IOSTANDARD = "LVCMOS33"; NET "fp_led_column_o[2]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[7]" IOSTANDARD = "LVCMOS33"; NET "fp_led_column_o[3]" IOSTANDARD = "LVCMOS33";
#---------------------------------------- #----------------------------------------
# 1-wire thermoeter + unique ID # 1-wire thermoeter + unique ID
......
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