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Simple VME FMC Carrier SVEC
Commit 8f2e30db authored by Federico Vaga's avatar Federico Vaga
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Merge branch '5-if-not-used-remove-the-rtl-golden' into 'master' 

Resolve "If not used remove the rtl/golden"

Closes #5

See merge request be-cem-edl/fec/hardware-modules/svec!6
parents de0f32b4 6539ff05
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hdl/.gitignore
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*~
*#
fifo_generator_v6_1
testbench/sfpga_bootloader/sample_bitstream/
*.*\#
\#*
.\#*
*.*~
syn/
work
*.wlf
modelsim.ini
transcript
*.vstf
*.bak
*.vcd
*.h
doc/
*.o
*.bin
*.elf
Makefile
Backup*.cdr
*.cmd
*.log
*.htm
*.html
*.vmf
*.bit
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hdl/rtl/bootloader/sfpga_bootloader.vhd
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......@@ -384,7 +384,6 @@ begin -- behavioral
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.stall <= '0';
wb_out.int <= '0';
regs_out <= regs_out_local or regs_out_flash;
U_WB_SLAVE : svec_xloader_wb
......
hdl/rtl/golden/Manifest.py deleted 100644 → 0
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
files = ["golden_core.vhd", "golden_wbgen2_pkg.vhd", "golden_wb.vhd", "golden_core_pkg.vhd"];
hdl/rtl/golden/golden_core.vhd deleted 100644 → 0
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gld_wbgen2_pkg.all;
entity golden_core is
generic(
g_slot_count : integer range 1 to 4);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
fmc_scl_o : out std_logic_vector(g_slot_count-1 downto 0);
fmc_sda_o : out std_logic_vector(g_slot_count-1 downto 0);
fmc_scl_i : in std_logic_vector(g_slot_count-1 downto 0);
fmc_sda_i : in std_logic_vector(g_slot_count-1 downto 0);
fmc_prsnt_n_i : in std_logic_vector(g_slot_count-1 downto 0)
);
end golden_core;
architecture rtl of golden_core is
component golden_wb
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_gld_in_registers;
regs_o : out t_gld_out_registers);
end component;
signal regs_in : t_gld_in_registers;
signal regs_out : t_gld_out_registers;
begin -- rtl
regs_in.csr_slot_count_i <= std_logic_vector(to_unsigned(g_slot_count, 4));
U_WB_Slave : golden_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => slave_i.adr(4 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
regs_i => regs_in,
regs_o => regs_out);
gen0 : if(g_slot_count >= 1) generate
fmc_scl_o(0) <= regs_out.i2cr0_scl_out_o;
fmc_sda_o(0) <= regs_out.i2cr0_sda_out_o;
regs_in.i2cr0_scl_in_i <= fmc_scl_i(0);
regs_in.i2cr0_sda_in_i <= fmc_sda_i(0);
regs_in.csr_fmc_present_i(0) <= not fmc_prsnt_n_i(0);
end generate gen0;
gen1 : if(g_slot_count >= 2) generate
fmc_scl_o(1) <= regs_out.i2cr1_scl_out_o;
fmc_sda_o(1) <= regs_out.i2cr1_sda_out_o;
regs_in.i2cr1_scl_in_i <= fmc_scl_i(1);
regs_in.i2cr1_sda_in_i <= fmc_sda_i(1);
regs_in.csr_fmc_present_i(1) <= not fmc_prsnt_n_i(1);
end generate gen1;
gen2 : if(g_slot_count >= 3) generate
fmc_scl_o(2) <= regs_out.i2cr2_scl_out_o;
fmc_sda_o(2) <= regs_out.i2cr2_sda_out_o;
regs_in.i2cr2_scl_in_i <= fmc_scl_i(2);
regs_in.i2cr2_sda_in_i <= fmc_sda_i(2);
regs_in.csr_fmc_present_i(2) <= not fmc_prsnt_n_i(2);
end generate gen2;
gen3 : if(g_slot_count >= 4) generate
fmc_scl_o(3) <= regs_out.i2cr3_scl_out_o;
fmc_sda_o(3) <= regs_out.i2cr3_sda_out_o;
regs_in.i2cr3_scl_in_i <= fmc_scl_i(3);
regs_in.i2cr3_sda_in_i <= fmc_sda_i(3);
regs_in.csr_fmc_present_i(3) <= not fmc_prsnt_n_i(3);
end generate gen3;
end rtl;
hdl/rtl/golden/golden_core_pkg.vhd deleted 100644 → 0
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package golden_core_pkg is
component golden_core
generic (
g_slot_count : integer range 1 to 4);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
fmc_scl_o : out std_logic_vector(g_slot_count-1 downto 0);
fmc_sda_o : out std_logic_vector(g_slot_count-1 downto 0);
fmc_scl_i : in std_logic_vector(g_slot_count-1 downto 0);
fmc_sda_i : in std_logic_vector(g_slot_count-1 downto 0);
fmc_prsnt_n_i : in std_logic_vector(g_slot_count-1 downto 0));
end component;
constant c_xwb_golden_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"676f6c64",
version => x"00000001",
date => x"20130516",
name => "WB-Golden-Core ")));
end golden_core_pkg;
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hdl/rtl/golden/golden_wb.wb deleted 100644 → 0
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Golden Bitstream WB Slave";
description = "A universal Golden Bitstream core for FMC carriers. Supports detection of up to 4 mezzanines";
hdl_entity = "golden_wb";
prefix = "gld";
reg {
name = "Control/Status reg";
prefix = "CSR";
field {
name = "Number of FMC slots";
description = "Number of FMC slots provided by this carrier";
prefix = "SLOT_COUNT";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC presence line status";
description = "State of presence lines in the respective slots (1 = mezzanine inserted). Bit N = mezzanine (N+1).";
prefix = "FMC_PRESENT";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 0";
prefix = "I2CR0";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 1";
prefix = "I2CR1";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 2";
prefix = "I2CR2";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 3";
prefix = "I2CR3";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
\ No newline at end of file
hdl/rtl/golden/golden_wbgen2_pkg.vhd deleted 100644 → 0
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Golden Bitstream WB Slave
---------------------------------------------------------------------------------------
-- File : golden_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from golden_wb.wb
-- Created : Mon Feb 3 14:32:23 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE golden_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package gld_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_gld_in_registers is record
csr_slot_count_i : std_logic_vector(3 downto 0);
csr_fmc_present_i : std_logic_vector(3 downto 0);
i2cr0_scl_in_i : std_logic;
i2cr0_sda_in_i : std_logic;
i2cr1_scl_in_i : std_logic;
i2cr1_sda_in_i : std_logic;
i2cr2_scl_in_i : std_logic;
i2cr2_sda_in_i : std_logic;
i2cr3_scl_in_i : std_logic;
i2cr3_sda_in_i : std_logic;
end record;
constant c_gld_in_registers_init_value: t_gld_in_registers := (
csr_slot_count_i => (others => '0'),
csr_fmc_present_i => (others => '0'),
i2cr0_scl_in_i => '0',
i2cr0_sda_in_i => '0',
i2cr1_scl_in_i => '0',
i2cr1_sda_in_i => '0',
i2cr2_scl_in_i => '0',
i2cr2_sda_in_i => '0',
i2cr3_scl_in_i => '0',
i2cr3_sda_in_i => '0'
);
-- Output registers (WB slave -> user design)
type t_gld_out_registers is record
i2cr0_scl_out_o : std_logic;
i2cr0_sda_out_o : std_logic;
i2cr1_scl_out_o : std_logic;
i2cr1_sda_out_o : std_logic;
i2cr2_scl_out_o : std_logic;
i2cr2_sda_out_o : std_logic;
i2cr3_scl_out_o : std_logic;
i2cr3_sda_out_o : std_logic;
end record;
constant c_gld_out_registers_init_value: t_gld_out_registers := (
i2cr0_scl_out_o => '0',
i2cr0_sda_out_o => '0',
i2cr1_scl_out_o => '0',
i2cr1_sda_out_o => '0',
i2cr2_scl_out_o => '0',
i2cr2_sda_out_o => '0',
i2cr3_scl_out_o => '0',
i2cr3_sda_out_o => '0'
);
function "or" (left, right: t_gld_in_registers) return t_gld_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body gld_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_gld_in_registers) return t_gld_in_registers is
variable tmp: t_gld_in_registers;
begin
tmp.csr_slot_count_i := f_x_to_zero(left.csr_slot_count_i) or f_x_to_zero(right.csr_slot_count_i);
tmp.csr_fmc_present_i := f_x_to_zero(left.csr_fmc_present_i) or f_x_to_zero(right.csr_fmc_present_i);
tmp.i2cr0_scl_in_i := f_x_to_zero(left.i2cr0_scl_in_i) or f_x_to_zero(right.i2cr0_scl_in_i);
tmp.i2cr0_sda_in_i := f_x_to_zero(left.i2cr0_sda_in_i) or f_x_to_zero(right.i2cr0_sda_in_i);
tmp.i2cr1_scl_in_i := f_x_to_zero(left.i2cr1_scl_in_i) or f_x_to_zero(right.i2cr1_scl_in_i);
tmp.i2cr1_sda_in_i := f_x_to_zero(left.i2cr1_sda_in_i) or f_x_to_zero(right.i2cr1_sda_in_i);
tmp.i2cr2_scl_in_i := f_x_to_zero(left.i2cr2_scl_in_i) or f_x_to_zero(right.i2cr2_scl_in_i);
tmp.i2cr2_sda_in_i := f_x_to_zero(left.i2cr2_sda_in_i) or f_x_to_zero(right.i2cr2_sda_in_i);
tmp.i2cr3_scl_in_i := f_x_to_zero(left.i2cr3_scl_in_i) or f_x_to_zero(right.i2cr3_scl_in_i);
tmp.i2cr3_sda_in_i := f_x_to_zero(left.i2cr3_sda_in_i) or f_x_to_zero(right.i2cr3_sda_in_i);
return tmp;
end function;
end package body;
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
target = "xilinx"
action = "simulation"
modules = { "local" : ["../../top/ddr_test/",
"testbench",
"sim_models/2048Mb_ddr3"]}
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vsim -novopt -t 1ps vme64x_ddr_tb
log -r /*
do wave_wb_buses.do
view wave
view transcript
run 50 us
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
files = ["ddr3.v"]
vlog_opt = "+incdir+sim_models/2048Mb_ddr3 +define+sg15E +define+x16"
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/****************************************************************************************
*
* File Name: ddr3_mcp.v
*
* Dependencies: ddr3.v, ddr3_parameters.vh
*
* Description: Micron SDRAM DDR3 (Double Data Rate 3) multi-chip package model
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
`timescale 1ps / 1ps
module ddr3_mcp (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`include "ddr3_parameters.vh"
// Declare Ports
input rst_n;
input ck;
input ck_n;
input [CS_BITS-1:0] cke;
input [CS_BITS-1:0] cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] tdqs_n;
input [CS_BITS-1:0] odt;
wire [RANKS-1:0] cke_mcp = cke;
wire [RANKS-1:0] cs_n_mcp = cs_n;
wire [RANKS-1:0] odt_mcp = odt;
ddr3 rank [RANKS-1:0] (
rst_n,
ck,
ck_n,
cke_mcp,
cs_n_mcp,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt_mcp
);
endmodule
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hdl/sim/ddr_test/sim_models/2048Mb_ddr3/readme.txt deleted 100644 → 0
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Disclaimer of Warranty:
-----------------------
This software code and all associated documentation, comments or other
information (collectively "Software") is provided "AS IS" without
warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES. Because some jurisdictions prohibit the exclusion or
limitation of liability for consequential or incidental damages, the
above limitation may not apply to you.
Copyright 2003 Micron Technology, Inc. All rights reserved.
Getting Started:
----------------
Unzip the included files to a folder.
Compile ddr3.v and tb.v in a verilog simulator.
Simulate the top level test bench tb.
Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
File Descriptions:
------------------
ddr3.v -ddr3 model
ddr3_mcp.v -structural wrapper for ddr3 - multi-chip package model
ddr3_module.v -structural wrapper for ddr3 - module model
ddr3_parameters.vh -file that contains all parameters used by the model
readme.txt -this file
tb.v -ddr3 model test bench
subtest.vh -example test included by the test bench.
tb.do -compiles and runs the ddr3 model and test bench
Defining the Speed Grade:
-------------------------
The verilog compiler directive "`define" may be used to choose between
multiple speed grades supported by the ddr3 model. Allowable speed
grades are listed in the ddr3_parameters.vh file and begin with the
letters "sg". The speed grade is used to select a set of timing
parameters for the ddr3 model. The following are examples of defining
the speed grade.
simulator command line
--------- ------------
ModelSim vlog +define+sg25 ddr3.v
VCS vcs +define+sg25 ddr3.v
NC-Verilog ncverilog +define+sg25 ddr3.v
Defining the Organization:
--------------------------
The verilog compiler directive "`define" may be used to choose between
multiple organizations supported by the ddr3 model. Valid
organizations include "x4", "x8", and x16, and are listed in the
ddr3_parameters.vh file. The organization is used to select the amount
of memory and the port sizes of the ddr3 model. The following are
examples of defining the organization.
simulator command line
--------- ------------
ModelSim vlog +define+x8 ddr3.v
NC-Verilog ncverilog +define+x8 ddr3.v
VCS vcs +define+x8 ddr3.v
All combinations of speed grade and organization are considered valid
by the ddr3 model even though a Micron part may not exist for every
combination.
Allocating Memory:
------------------
An associative array has been implemented to reduce the amount of
static memory allocated by the ddr3 model. Each entry in the
associative array is a burst length of eight in size. The number of
entries in the associative array is controlled by the MEM_BITS
parameter, and is equal to 2^MEM_BITS. For example, if the MEM_BITS
parameter is equal to 10, the associative array will be large enough
to store 1024 writes of burst length 8 to unique addresses. The
following are examples of setting the MEM_BITS parameter to 8.
simulator command line
--------- ------------
ModelSim vsim -GMEM_BITS=8 ddr3
NC-Verilog ncverilog +defparam+ddr3.MEM_BITS=8 ddr3.v
VCS vcs -pvalue+MEM_BITS=8 ddr3.v
It is possible to allocate memory for every address supported by the
ddr3 model by using the verilog compiler directive "`define MAX_MEM".
This procedure will improve simulation performance at the expense of
system memory. The following are examples of allocating memory for
every address.
Simulator command line
--------- ------------
ModelSim vlog +define+MAX_MEM ddr3.v
NC-Verilog ncverilog +define+MAX_MEM ddr3.v
VCS vcs +define+MAX_MEM ddr3.v
**********************************************************************
The following information is provided to assist the modeling engineer
in creating multi-chip package (mcp) models. ddr3_mcp.v is a
structural wrapper that instantiates ddr3 models. This wrapper can be
used to create single, dual, or quad rank mcp models. From the
perspective of the model, the only item that needs to be defined is the
number of ranks.
**********************************************************************
Defining the Number of Ranks in a multi-chip package:
----------------------------------------------------
The verilog compiler directive "`define" may be used to choose between
single, dual, and quad rank mcp configurations. The default is single
rank if nothing is defined. Dual rank configuration can be selected by
defining "DUAL_RANK" when the ddr3_mcp is compiled. Quad rank
configuration can be selected by defining "QUAD_RANK" when the ddr3_mcp
is compiled. The following are examples of defining a dual rank mcp
configuration.
simulator command line
--------- ------------
ModelSim vlog +define+DUAL_RANK ddr3.v ddr3_mcp.v
NC-Verilog ncverilog +define+DUAL_RANK ddr3.v ddr3_mcp.v
VCS vcs +define+DUAL_RANK ddr3.v ddr3_mcp.v
**********************************************************************
The following information is provided to assist the modeling engineer
in creating DIMM models. ddr3_module.v is a structural wrapper that
instantiates ddr3 models. This wrapper can be used to create UDIMM,
RDIMM or SODIMM models. Other form factors are not supported
(MiniDIMM, VLP DIMM, etc.). From the perspective of the model, the
items that need to be defined are the number of ranks, the module
type, and the presence of ECC. All combinations of ranks, module
type, and ECC are considered valid by the ddr3_module model even
though a Micron part may not exist for every combination.
**********************************************************************
Defining the Number of Ranks on a module:
----------------------------------------
The verilog compiler directive "`define" may be used to choose between
single, dual, and quad rank module configurations. The default is single
rank if nothing is defined. Dual rank configuration can be selected by
defining "DUAL_RANK" when the ddr3_module is compiled. Quad rank
configuration can be selected by defining "QUAD_RANK" when the ddr3_module
is compiled. The following are examples of defining a dual rank module
configuration.
simulator command line
--------- ------------
ModelSim vlog +define+DUAL_RANK ddr3.v ddr3_module.v
NC-Verilog ncverilog +define+DUAL_RANK ddr3.v ddr3_module.v
VCS vcs +define+DUAL_RANK ddr3.v ddr3_module.v
Defining the Module Type:
-----------------------------------
The verilog compiler directive "`define" may be used to choose between
UDIMM, RDIMM, and SODIMM module configurations. The default is
unregistered (UDIMM) if nothing is defined. SODIMM configuration can be
selected by defining "SODIMM" when the ddr3_module is compiled. Registered
configuration can be selected by defining "RDIMM" when the ddr3_module is
compiled. The following are examples of defining a registered module
configuration.
simulator command line
--------- ------------
ModelSim vlog +define+RDIMM ddr3.v ddr3_module.v
NC-Verilog ncverilog +define+RDIMM ddr3.v ddr3_module.v
VCS vcs +define+RDIMM ddr3.v ddr3_module.v
Defining the ECC for a module:
-----------------------------
The verilog compiler directive "`define" may be used to choose between
ECC and nonECC module configurations. The default is nonECC if nothing
is defined. ECC configuration can be selected by defining "ECC" when
the ddr3_module is compiled. The following are examples of defining an
ECC module configuration.
simulator command line
--------- ------------
ModelSim vlog +define+ECC ddr3.v ddr3_module.v
NC-Verilog ncverilog +define+ECC ddr3.v ddr3_module.v
VCS vcs +define+ECC ddr3.v ddr3_module.v
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#########################################################################################
#
# Disclaimer This software code and all associated documentation, comments or other
# of Warranty: information (collectively "Software") is provided "AS IS" without
# warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
# DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
# TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
# OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
# WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
# OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
# FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
# THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
# ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
# OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
# ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
# INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
# WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
# OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
# THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
# DAMAGES. Because some jurisdictions prohibit the exclusion or
# limitation of liability for consequential or incidental damages, the
# above limitation may not apply to you.
#
# Copyright 2003 Micron Technology, Inc. All rights reserved.
#
#########################################################################################
vlog -novopt ddr3.v tb.v
vsim -novopt tb
add wave -p sdramddr3/*
run -all
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
files = [ "VME64x_Package.vhd",
"VME64x_SIM_Package.vhd",
"vme64x_ddr_tb.vhd" ]
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--------------------------------------------------------------------------------------
---------------------------VME64x_Package-----------------------------------------
--------------------------------------------------------------------------------------
-- Date : Fri Mar 03 2012
--
-- Author : Davide Pedretti
--
-- Company : CERN
--
-- Description : VME64x constants, records, type...
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.all;
use work.vme64x_pack.all;
package VME64x is
subtype Vme64xAddressType is std_logic_vector(31 downto 1); -- (31 downto 0)
subtype Vme64xDataType is std_logic_vector(31 downto 0);
subtype Vme64xAddressModType is std_logic_vector(5 downto 0);
type VME64xBusOut_Record is -- This is an output for the VME64x master
record
Vme64xAsN : std_logic;
Vme64xDs1N : std_logic;
Vme64xDs0N : std_logic;
Vme64xLWORDN : std_logic;
Vme64xIACK : std_logic;
Vme64xIACKIN : std_logic;
Vme64xWRITEN : std_logic;
Vme64xAM : Vme64xAddressModType;
Vme64xADDR : Vme64xAddressType;
Vme64xDATA : Vme64xDataType;
end record;
type VME64xBusIn_Record is -- This is an input for the VME64x master
record
Vme64xDtackN : std_logic;
Vme64xBerrN : std_logic;
Vme64xRetryN : std_logic;
Vme64xADDR : Vme64xAddressType;
Vme64xDATA : Vme64xDataType;
Vme64xLWORDN : std_logic;
Vme64xIACKOUT : std_logic;
Vme64xIRQ : std_logic_vector(6 downto 0);
end record;
-- Types
type t_Buffer_BLT is array (0 to 66) of std_logic_vector(31 downto 0); -- for BLT transfer
--The buffer has 65 positions, not 64; the last position is for test the error if i transfer more of 256 bytes.
type t_Buffer_MBLT is array (0 to 258) of std_logic_vector(63 downto 0); -- for MBLT transfer
--The buffer has 258 positions, not 256; the last position is for test the error if i transfer more of 256 bytes.
type t_dataTransferType is (D08Byte0, D08Byte1, D08Byte2, D08Byte3, D16Byte01, D16Byte23, D32); -- for D64 use dataTransferType D32!
type t_Addressing_Type is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LCK, A32, A32_BLT, A32_MBLT, A32_LCK,
A64, A64_BLT, A64_MBLT, A64_LCK, A32_2eVME, A64_2eVME, A32_2eSST, A64_2eSST, error);
-- Declare constants
-- constant <constant_name> : time := <time_unit> ns;
constant BA : std_logic_vector(7 downto 0) := "11110000";
constant VME_GA : std_logic_vector(5 downto 0) := "110111"; -- GA parity match '1' & slot number
constant ID_Master : std_logic_vector(7 downto 0) := "00001111"; -- max 31
constant ADER0_A16_S : std_logic_vector(31 downto 0) := "0000000000000000" & BA(7 downto 3) & "000" & c_A16 &"00";
constant ADER0_A24_S : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_S &"00";
constant ADER0_A24_BLT : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_BLT &"00";
constant ADER0_A24_MBLT : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_MBLT &"00";
constant ADER0_A32 : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32 &"00";
constant ADER0_A32_BLT : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32_BLT &"00";
constant ADER0_A32_MBLT : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32_MBLT &"00";
constant ADER1_A64 : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64 &"00";
constant ADER1_A64_BLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_BLT &"00";
constant ADER1_A64_MBLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_MBLT &"00";
constant ADER1_A64_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "000000000000000000000000000";
constant ADER2_A32_2eVME : std_logic_vector(31 downto 0) := BA(7 downto 3) & "00000000000000000" & x"01" &"01";
constant ADER2_A64_2eVME : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"02" &"01";
constant ADER2_A32_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"11" &"01";
constant ADER2_A64_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"12" &"01";
constant ADER2_2e_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "000000000000000000000000000";
-- CSR constants
constant c_BAR : std_logic_vector := x"7FFFF";
constant c_BIT_SET_REG : std_logic_vector := x"7FFFB";
constant c_BIT_CLR_REG : std_logic_vector := x"7FFF7";
constant c_CRAM_OWNER : std_logic_vector := x"7FFF3";
constant c_USR_BIT_SET_REG : std_logic_vector := x"7FFEF";
constant c_USR_BIT_CLR_REG : std_logic_vector := x"7FFEB";
constant c_FUNC7_ADER_0 : std_logic_vector := x"7FFDF";
constant c_FUNC7_ADER_1 : std_logic_vector := x"7FFDB";
constant c_FUNC7_ADER_2 : std_logic_vector := x"7FFD7";
constant c_FUNC7_ADER_3 : std_logic_vector := x"7FFD3";
constant c_FUNC6_ADER_0 : std_logic_vector := x"7FFCF";
constant c_FUNC6_ADER_1 : std_logic_vector := x"7FFCB";
constant c_FUNC6_ADER_2 : std_logic_vector := x"7FFC7";
constant c_FUNC6_ADER_3 : std_logic_vector := x"7FFC3";
constant c_FUNC5_ADER_0 : std_logic_vector := x"7FFBF";
constant c_FUNC5_ADER_1 : std_logic_vector := x"7FFBB";
constant c_FUNC5_ADER_2 : std_logic_vector := x"7FFB7";
constant c_FUNC5_ADER_3 : std_logic_vector := x"7FFB3";
constant c_FUNC4_ADER_0 : std_logic_vector := x"7FFAF";
constant c_FUNC4_ADER_1 : std_logic_vector := x"7FFAB";
constant c_FUNC4_ADER_2 : std_logic_vector := x"7FFA7";
constant c_FUNC4_ADER_3 : std_logic_vector := x"7FFA3";
constant c_FUNC3_ADER_0 : std_logic_vector := x"7FF9F";
constant c_FUNC3_ADER_1 : std_logic_vector := x"7FF9B";
constant c_FUNC3_ADER_2 : std_logic_vector := x"7FF97";
constant c_FUNC3_ADER_3 : std_logic_vector := x"7FF93";
constant c_FUNC2_ADER_0 : std_logic_vector := x"7FF8F";
constant c_FUNC2_ADER_1 : std_logic_vector := x"7FF8B";
constant c_FUNC2_ADER_2 : std_logic_vector := x"7FF87";
constant c_FUNC2_ADER_3 : std_logic_vector := x"7FF83";
constant c_FUNC1_ADER_0 : std_logic_vector := x"7FF7F";
constant c_FUNC1_ADER_1 : std_logic_vector := x"7FF7B";
constant c_FUNC1_ADER_2 : std_logic_vector := x"7FF77";
constant c_FUNC1_ADER_3 : std_logic_vector := x"7FF73";
constant c_FUNC0_ADER_0 : std_logic_vector := x"7FF6F";
constant c_FUNC0_ADER_1 : std_logic_vector := x"7FF6B";
constant c_FUNC0_ADER_2 : std_logic_vector := x"7FF67";
constant c_FUNC0_ADER_3 : std_logic_vector := x"7FF63";
constant c_BYTES0 : std_logic_vector := x"7FF3b";
constant c_MBLT_Endian : std_logic_vector := x"7Ff53";
constant c_IRQ_Vector : std_logic_vector := x"7FF5F";
constant c_IRQ_level : std_logic_vector := x"7FF5B";
constant c_WB32or64 : std_logic_vector := x"7FF33";
-- CR constant
constant c_StartDefinedCR : std_logic_vector := x"00000";
constant c_EndDefinedCR : std_logic_vector := x"00FFF";
end VME64x;
package body VME64x is
end VME64x;
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /vme64x_ddr_tb/rst_n_i
add wave -noupdate /vme64x_ddr_tb/VME_RST_n_i
add wave -noupdate /vme64x_ddr_tb/uut/sys_rst_n
add wave -noupdate /vme64x_ddr_tb/clk_i
add wave -noupdate -divider VME
add wave -noupdate /vme64x_ddr_tb/VME_BERR_o
add wave -noupdate /vme64x_ddr_tb/VME_DS_n_i
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/VME_DATA_b
add wave -noupdate /vme64x_ddr_tb/VME_AS_n_i
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/VME_ADDR_b
add wave -noupdate /vme64x_ddr_tb/VME_LWORD_n_b
add wave -noupdate /vme64x_ddr_tb/VME_WRITE_n_i
add wave -noupdate /vme64x_ddr_tb/VME_DTACK_n_o
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/s_dataToReceive
add wave -noupdate -divider {Master WB}
add wave -noupdate /vme64x_ddr_tb/uut/wbm_we
add wave -noupdate /vme64x_ddr_tb/uut/wbm_stb
add wave -noupdate /vme64x_ddr_tb/uut/wbm_stall
add wave -noupdate /vme64x_ddr_tb/uut/wbm_sel
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/wbm_dat_o
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/wbm_dat_i
add wave -noupdate /vme64x_ddr_tb/uut/wbm_cyc
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/wbm_adr
add wave -noupdate /vme64x_ddr_tb/uut/wbm_ack
add wave -noupdate -divider {Slaves WB}
add wave -noupdate /vme64x_ddr_tb/uut/wb_we
add wave -noupdate /vme64x_ddr_tb/uut/wb_stb
add wave -noupdate /vme64x_ddr_tb/uut/wb_stall
add wave -noupdate /vme64x_ddr_tb/uut/wb_sel
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/wb_dat_o
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/wb_dat_i
add wave -noupdate /vme64x_ddr_tb/uut/wb_cyc
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/wb_adr
add wave -noupdate /vme64x_ddr_tb/uut/wb_ack
add wave -noupdate -divider {DDR bank4}
add wave -noupdate /vme64x_ddr_tb/uut/sys_clk
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/ddr_bank4_addr_cnt
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_we_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_we_d
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_stb_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_stb_d
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_cyc_r_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_cyc_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_cyc_d
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_wr_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_wr_data
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_rd_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_rd_data_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_cmd_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
add wave -noupdate -divider {DDR bank5}
add wave -noupdate /vme64x_ddr_tb/uut/ddr_bank5_addr_cnt
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_we_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_we_d
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_stb_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_stb_d
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_cyc_r_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_cyc_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_cyc_d
add wave -noupdate /vme64x_ddr_tb/uut/ddr3_bank5_status(0)
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_wr_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_wr_data
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_rd_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_rd_data_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_cmd_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {17413525 ps} 0}
configure wave -namecolwidth 505
configure wave -valuecolwidth 203
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {17207022 ps} {17844969 ps}
hdl/sim/flash/M25P128.v deleted 100644 → 0
View file @ de0f32b4
This diff is collapsed.
hdl/sim/regs/golden_regs.vh deleted 100644 → 0
View file @ de0f32b4
`define ADDR_GLD_CSR 5'h0
`define GLD_CSR_SLOT_COUNT_OFFSET 0
`define GLD_CSR_SLOT_COUNT 32'h0000000f
`define GLD_CSR_FMC_PRESENT_OFFSET 4
`define GLD_CSR_FMC_PRESENT 32'h000000f0
`define ADDR_GLD_I2CR0 5'h4
`define GLD_I2CR0_SCL_OUT_OFFSET 0
`define GLD_I2CR0_SCL_OUT 32'h00000001
`define GLD_I2CR0_SDA_OUT_OFFSET 1
`define GLD_I2CR0_SDA_OUT 32'h00000002
`define GLD_I2CR0_SCL_IN_OFFSET 2
`define GLD_I2CR0_SCL_IN 32'h00000004
`define GLD_I2CR0_SDA_IN_OFFSET 3
`define GLD_I2CR0_SDA_IN 32'h00000008
`define ADDR_GLD_I2CR1 5'h8
`define GLD_I2CR1_SCL_OUT_OFFSET 0
`define GLD_I2CR1_SCL_OUT 32'h00000001
`define GLD_I2CR1_SDA_OUT_OFFSET 1
`define GLD_I2CR1_SDA_OUT 32'h00000002
`define GLD_I2CR1_SCL_IN_OFFSET 2
`define GLD_I2CR1_SCL_IN 32'h00000004
`define GLD_I2CR1_SDA_IN_OFFSET 3
`define GLD_I2CR1_SDA_IN 32'h00000008
`define ADDR_GLD_I2CR2 5'hc
`define GLD_I2CR2_SCL_OUT_OFFSET 0
`define GLD_I2CR2_SCL_OUT 32'h00000001
`define GLD_I2CR2_SDA_OUT_OFFSET 1
`define GLD_I2CR2_SDA_OUT 32'h00000002
`define GLD_I2CR2_SCL_IN_OFFSET 2
`define GLD_I2CR2_SCL_IN 32'h00000004
`define GLD_I2CR2_SDA_IN_OFFSET 3
`define GLD_I2CR2_SDA_IN 32'h00000008
`define ADDR_GLD_I2CR3 5'h10
`define GLD_I2CR3_SCL_OUT_OFFSET 0
`define GLD_I2CR3_SCL_OUT 32'h00000001
`define GLD_I2CR3_SDA_OUT_OFFSET 1
`define GLD_I2CR3_SDA_OUT 32'h00000002
`define GLD_I2CR3_SCL_IN_OFFSET 2
`define GLD_I2CR3_SCL_IN 32'h00000004
`define GLD_I2CR3_SDA_IN_OFFSET 3
`define GLD_I2CR3_SDA_IN 32'h00000008
hdl/sim/regs/sxldr_regs.vh deleted 100644 → 0
View file @ de0f32b4
`define ADDR_SXLDR_CSR 5'h0
`define SXLDR_CSR_START_OFFSET 0
`define SXLDR_CSR_START 32'h00000001
`define SXLDR_CSR_DONE_OFFSET 1
`define SXLDR_CSR_DONE 32'h00000002
`define SXLDR_CSR_ERROR_OFFSET 2
`define SXLDR_CSR_ERROR 32'h00000004
`define SXLDR_CSR_BUSY_OFFSET 3
`define SXLDR_CSR_BUSY 32'h00000008
`define SXLDR_CSR_MSBF_OFFSET 4
`define SXLDR_CSR_MSBF 32'h00000010
`define SXLDR_CSR_SWRST_OFFSET 5
`define SXLDR_CSR_SWRST 32'h00000020
`define SXLDR_CSR_EXIT_OFFSET 6
`define SXLDR_CSR_EXIT 32'h00000040
`define SXLDR_CSR_CLKDIV_OFFSET 8
`define SXLDR_CSR_CLKDIV 32'h00003f00
`define SXLDR_CSR_VERSION_OFFSET 14
`define SXLDR_CSR_VERSION 32'h003fc000
`define ADDR_SXLDR_BTRIGR 5'h4
`define ADDR_SXLDR_FAR 5'h8
`define SXLDR_FAR_DATA_OFFSET 0
`define SXLDR_FAR_DATA 32'h000000ff
`define SXLDR_FAR_XFER_OFFSET 8
`define SXLDR_FAR_XFER 32'h00000100
`define SXLDR_FAR_READY_OFFSET 9
`define SXLDR_FAR_READY 32'h00000200
`define SXLDR_FAR_CS_OFFSET 10
`define SXLDR_FAR_CS 32'h00000400
`define ADDR_SXLDR_IDR 5'hc
`define ADDR_SXLDR_FIFO_R0 5'h10
`define SXLDR_FIFO_R0_XSIZE_OFFSET 0
`define SXLDR_FIFO_R0_XSIZE 32'h00000003
`define SXLDR_FIFO_R0_XLAST_OFFSET 2
`define SXLDR_FIFO_R0_XLAST 32'h00000004
`define ADDR_SXLDR_FIFO_R1 5'h14
`define SXLDR_FIFO_R1_XDATA_OFFSET 0
`define SXLDR_FIFO_R1_XDATA 32'hffffffff
`define ADDR_SXLDR_FIFO_CSR 5'h18
`define SXLDR_FIFO_CSR_FULL_OFFSET 16
`define SXLDR_FIFO_CSR_FULL 32'h00010000
`define SXLDR_FIFO_CSR_EMPTY_OFFSET 17
`define SXLDR_FIFO_CSR_EMPTY 32'h00020000
`define SXLDR_FIFO_CSR_CLEAR_BUS_OFFSET 18
`define SXLDR_FIFO_CSR_CLEAR_BUS 32'h00040000
`define SXLDR_FIFO_CSR_USEDW_OFFSET 0
`define SXLDR_FIFO_CSR_USEDW 32'h000000ff
hdl/sim/vme64x_bfm/components/sn74vmeh22501.v deleted 100644 → 0
View file @ de0f32b4
`timescale 1ns/1ns
module sn74vmeh22501 (
input oeab1,
oeby1_n,
a1,
output y1,
inout b1,
input oeab2,
oeby2_n,
a2,
output y2,
inout b2,
input oe_n,
input dir,
clkab,
le,
clkba,
inout [1:8] a3,
inout [1:8] b3);
assign b1 = oeab1 ? a1 : 1'bz;
assign y1 = oeby1_n ? 1'bz : b1;
assign b2 = oeab2 ? a2 : 1'bz;
assign y2 = oeby2_n ? 1'bz : b2;
reg [1:8] b3LFF;
always @(posedge clkab) if (~le) b3LFF <= #1 a3;
always @* if (le) b3LFF = a3;
assign b3 = (~oe_n && dir) ? b3LFF : 8'hz;
reg [1:8] a3LFF;
always @(posedge clkba) if (~le) a3LFF <= #1 b3;
always @* if (le) a3LFF = b3;
assign a3 = (~oe_n && ~dir) ? a3LFF : 8'hz;
endmodule
hdl/sim/vme64x_bfm/svec_vme_buffers.svh deleted 100644 → 0
View file @ de0f32b4
`include "components/sn74vmeh22501.v"
`include "vme64x_bfm.svh"
module bidir_buf(
a,
b,
dir, /* 0: a->b, 1: b->a */
oe_n );
parameter g_width = 1;
inout [g_width-1:0] a,b;
input dir, oe_n;
assign b = (!dir && !oe_n) ? a : 'bz;
assign a = (dir && !oe_n) ? b : 'bz;
endmodule // bidir_buf
module svec_vme_buffers (
output VME_AS_n_o,
output VME_RST_n_o,
output VME_WRITE_n_o,
output [5:0] VME_AM_o,
output [1:0] VME_DS_n_o,
output [5:0] VME_GA_o,
input VME_BERR_i,
input VME_DTACK_n_i,
input VME_RETRY_n_i,
input VME_RETRY_OE_i,
inout VME_LWORD_n_b,
inout [31:1] VME_ADDR_b,
inout [31:0] VME_DATA_b,
output VME_BBSY_n_o,
input [6:0] VME_IRQ_n_i,
output VME_IACKIN_n_o,
input VME_IACKOUT_n_i,
output VME_IACK_n_o,
input VME_DTACK_OE_i,
input VME_DATA_DIR_i,
input VME_DATA_OE_N_i,
input VME_ADDR_DIR_i,
input VME_ADDR_OE_N_i,
IVME64X.slave slave
);
pullup(slave.as_n);
pullup(slave.rst_n);
pullup(slave.irq_n[0]);
pullup(slave.irq_n[1]);
pullup(slave.irq_n[2]);
pullup(slave.irq_n[3]);
pullup(slave.irq_n[4]);
pullup(slave.irq_n[5]);
pullup(slave.irq_n[6]);
pullup(slave.iack_n);
pullup(slave.dtack_n);
pullup(slave.retry_n);
pullup(slave.ds_n[1]);
pullup(slave.ds_n[0]);
pullup(slave.lword_n);
pullup(slave.berr_n);
pullup(slave.write_n);
pulldown(slave.bbsy_n);
pullup(slave.iackin_n);
assign VME_RST_n_o = slave.rst_n;
assign VME_AS_n_o = slave.as_n;
assign VME_GA_o = slave.ga;
assign VME_WRITE_n_o = slave.write_n;
assign VME_AM_o = slave.am;
assign VME_DS_n_o = slave.ds_n;
assign VME_BBSY_n_o = slave.bbsy_n;
assign VME_IACKIN_n_o = slave.iackin_n;
assign VME_IACK_n_o = slave.iack_n;
bidir_buf #(1) b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(31) b1 (slave.addr, VME_ADDR_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(33) b2 (slave.data, VME_DATA_b, VME_DATA_DIR_i, VME_DATA_OE_N_i);
pulldown(VME_BERR_i);
pulldown(VME_ADDR_DIR_i);
pulldown(VME_ADDR_OE_N_i);
pulldown(VME_DATA_DIR_i);
pulldown(VME_DATA_OE_N_i);
assign slave.dtack_n = VME_DTACK_n_i;
assign slave.berr_n = ~VME_BERR_i;
assign slave.retry_n = VME_RETRY_n_i;
endmodule
`define DECLARE_VME_BUFFERS(iface) \
wire VME_AS_n;\
wire VME_RST_n;\
wire VME_WRITE_n;\
wire [5:0] VME_AM;\
wire [1:0] VME_DS_n;\
wire VME_BERR;\
wire VME_DTACK_n;\
wire VME_RETRY_n;\
wire VME_RETRY_OE;\
wire VME_LWORD_n;\
wire [31:1]VME_ADDR;\
wire [31:0]VME_DATA;\
wire VME_BBSY_n;\
wire [6:0]VME_IRQ_n;\
wire VME_IACKIN_n,VME_IACK_n;\
wire VME_IACKOUT_n;\
wire VME_DTACK_OE;\
wire VME_DATA_DIR;\
wire VME_DATA_OE_N;\
wire VME_ADDR_DIR;\
wire VME_ADDR_OE_N;\
svec_vme_buffers U_VME_Bufs ( \
.VME_AS_n_o(VME_AS_n),\
.VME_RST_n_o(VME_RST_n),\
.VME_WRITE_n_o(VME_WRITE_n),\
.VME_AM_o(VME_AM),\
.VME_DS_n_o(VME_DS_n),\
.VME_BERR_i(VME_BERR),\
.VME_DTACK_n_i(VME_DTACK_n),\
.VME_RETRY_n_i(VME_RETRY_n),\
.VME_RETRY_OE_i(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_o(VME_BBSY_n),\
.VME_IRQ_n_i(VME_IRQ_n),\
.VME_IACK_n_o(VME_IACK_n),\
.VME_IACKIN_n_o(VME_IACKIN_n),\
.VME_IACKOUT_n_i(VME_IACKOUT_n),\
.VME_DTACK_OE_i(VME_DTACK_OE),\
.VME_DATA_DIR_i(VME_DATA_DIR),\
.VME_DATA_OE_N_i(VME_DATA_OE_N),\
.VME_ADDR_DIR_i(VME_ADDR_DIR),\
.VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
.slave(iface)\
);
function automatic bit[5:0] _gen_ga(int slot);
bit[4:0] slot_id = slot;
return {^slot_id, ~slot_id};
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_RST_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_i(VME_BBSY_n),\
.VME_IRQ_n_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
\ No newline at end of file
hdl/sim/vme64x_bfm/vme64x_bfm.svh deleted 100644 → 0
View file @ de0f32b4
This diff is collapsed.
hdl/platform/Manifest.py → hdl/syn/common/.gitignore
View file @ 8f2e30db
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
# SPDX-License-Identifier: CERN-OHL-W-2.0+
files =["chipscope_icon.ngc", "chipscope_ila.ngc" ]
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/common/svec_base_common.ucf
View file @ 8f2e30db
......@@ -234,7 +234,7 @@ NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "ref_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
......
hdl/syn/golden/.gitignore 0 → 100644
View file @ 8f2e30db
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/sfpga_bootloader/.gitignore 0 → 100644
View file @ 8f2e30db
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/sfpga_bootloader/Manifest.py
View file @ 8f2e30db
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
# SPDX-License-Identifier: CERN-OHL-W-2.0+
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
# fetchto variable independent of where those Manifests reside in the filesystem.
import os
fetchto = os.path.abspath(fetchto)
syn_device = "xc6slx9"
syn_grade = "-2"
......@@ -14,4 +22,13 @@ syn_top = "svec_sfpga_top"
syn_project = "svec_sfpga.xise"
syn_tool = "ise"
modules = { "local" : [ "../../top/sfpga_bootloader", "../../platform" ] }
files = [ "svec_sfpga_top.ucf" ]
modules = {
"local" : [
"../../top/sfpga_bootloader",
],
"git" : [
"https://ohwr.org/project/general-cores.git",
],
}
hdl/syn/wr_example/.gitignore 0 → 100644
View file @ 8f2e30db
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/golden_wr/Manifest.py → hdl/syn/wr_example/Manifest.py
View file @ 8f2e30db
......@@ -18,9 +18,9 @@ fetchto = os.path.abspath(fetchto)
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_project = "svec_golden_wr.xise"
syn_project = "svec_base_wr_example.xise"
syn_tool = "ise"
syn_top = "svec_golden_wr"
syn_top = "svec_base_wr_example"
board = "svec"
ctrls = ["bank4_64b_32b"]
......@@ -31,7 +31,7 @@ files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr",
"../../top/wr_example",
"../../syn/common",
],
"git" : [
......
hdl/testbench/golden/.gitignore 0 → 100644
View file @ 8f2e30db
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
work/
Makefile
modelsim.ini
transcript*
*.wlf
buildinfo_pkg.vhd
hdl/testbench/golden/Manifest.py
View file @ 8f2e30db
......@@ -4,10 +4,45 @@
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/wb"
sim_tool = "modelsim"
sim_top = "main"
vcom_opt = "-93 -mixedsvvh"
files = [ "main.sv" ]
syn_device = "xc6slx150t"
board = "svec"
modules = { "local" : [ "../../top/golden" ] }
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
# fetchto variable independent of where those Manifests reside in the filesystem.
import os
fetchto = os.path.abspath(fetchto)
include_dirs = [
"../include",
fetchto + "/vme64x-core/hdl/sim/vme64x_bfm",
fetchto + "/general-cores/sim",
]
files = [ "main.sv", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../top/golden" ],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/golden/main.sv
View file @ 8f2e30db
This diff is collapsed.
hdl/testbench/template/run.do → hdl/testbench/golden/run.do
View file @ 8f2e30db
vsim -quiet -t 10fs -L unisim work.main -novopt
vsim -quiet -t 10fs -L unisim work.main
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......@@ -7,6 +7,4 @@ radix -hexadecimal
log -r /*
run 1us
wave zoomfull
run -all
hdl/testbench/golden/wave.do deleted 100644 → 0
View file @ de0f32b4
This diff is collapsed.
hdl/testbench/include/svec_base_regs.svh 0 → 100644
View file @ 8f2e30db
package svec_base_regs_Consts;
localparam SVEC_BASE_REGS_SIZE = 16384;
localparam ADDR_SVEC_BASE_REGS_METADATA = 'h0;
localparam ADDR_MASK_SVEC_BASE_REGS_METADATA = 'h3fc0;
localparam SVEC_BASE_REGS_METADATA_SIZE = 64;
localparam ADDR_SVEC_BASE_REGS_CSR = 'h40;
localparam SVEC_BASE_REGS_CSR_SIZE = 32;
localparam ADDR_SVEC_BASE_REGS_CSR_APP_OFFSET = 'h40;
localparam ADDR_SVEC_BASE_REGS_CSR_RESETS = 'h44;
localparam SVEC_BASE_REGS_CSR_RESETS_GLOBAL_OFFSET = 0;
localparam SVEC_BASE_REGS_CSR_RESETS_GLOBAL = 32'h1;
localparam SVEC_BASE_REGS_CSR_RESETS_APPL_OFFSET = 1;
localparam SVEC_BASE_REGS_CSR_RESETS_APPL = 32'h2;
localparam ADDR_SVEC_BASE_REGS_CSR_FMC_PRESENCE = 'h48;
localparam ADDR_SVEC_BASE_REGS_CSR_UNUSED0 = 'h4c;
localparam SVEC_BASE_REGS_CSR_UNUSED0_PRESET = 32'h0;
localparam ADDR_SVEC_BASE_REGS_CSR_DDR_STATUS = 'h50;
localparam SVEC_BASE_REGS_CSR_DDR_STATUS_DDR4_CALIB_DONE_OFFSET = 0;
localparam SVEC_BASE_REGS_CSR_DDR_STATUS_DDR4_CALIB_DONE = 32'h1;
localparam SVEC_BASE_REGS_CSR_DDR_STATUS_DDR5_CALIB_DONE_OFFSET = 1;
localparam SVEC_BASE_REGS_CSR_DDR_STATUS_DDR5_CALIB_DONE = 32'h2;
localparam ADDR_SVEC_BASE_REGS_CSR_PCB_REV = 'h54;
localparam SVEC_BASE_REGS_CSR_PCB_REV_REV_OFFSET = 0;
localparam SVEC_BASE_REGS_CSR_PCB_REV_REV = 32'h1f;
localparam ADDR_SVEC_BASE_REGS_CSR_DDR4_ADDR = 'h58;
localparam ADDR_SVEC_BASE_REGS_CSR_DDR5_ADDR = 'h5c;
localparam ADDR_SVEC_BASE_REGS_THERM_ID = 'h80;
localparam ADDR_MASK_SVEC_BASE_REGS_THERM_ID = 'h3ff0;
localparam SVEC_BASE_REGS_THERM_ID_SIZE = 16;
localparam ADDR_SVEC_BASE_REGS_FMC_I2C = 'ha0;
localparam ADDR_MASK_SVEC_BASE_REGS_FMC_I2C = 'h3fe0;
localparam SVEC_BASE_REGS_FMC_I2C_SIZE = 32;
localparam ADDR_SVEC_BASE_REGS_FLASH_SPI = 'hc0;
localparam ADDR_MASK_SVEC_BASE_REGS_FLASH_SPI = 'h3fe0;
localparam SVEC_BASE_REGS_FLASH_SPI_SIZE = 32;
localparam ADDR_SVEC_BASE_REGS_VIC = 'h100;
localparam ADDR_MASK_SVEC_BASE_REGS_VIC = 'h3f00;
localparam SVEC_BASE_REGS_VIC_SIZE = 256;
localparam ADDR_SVEC_BASE_REGS_BUILDINFO = 'h200;
localparam ADDR_MASK_SVEC_BASE_REGS_BUILDINFO = 'h3f00;
localparam SVEC_BASE_REGS_BUILDINFO_SIZE = 256;
localparam ADDR_SVEC_BASE_REGS_WRC_REGS = 'h1000;
localparam ADDR_MASK_SVEC_BASE_REGS_WRC_REGS = 'h3800;
localparam SVEC_BASE_REGS_WRC_REGS_SIZE = 2048;
localparam ADDR_SVEC_BASE_REGS_DDR4_DATA = 'h2000;
localparam ADDR_MASK_SVEC_BASE_REGS_DDR4_DATA = 'h3000;
localparam SVEC_BASE_REGS_DDR4_DATA_SIZE = 4096;
localparam ADDR_SVEC_BASE_REGS_DDR5_DATA = 'h3000;
localparam ADDR_MASK_SVEC_BASE_REGS_DDR5_DATA = 'h3000;
localparam SVEC_BASE_REGS_DDR5_DATA_SIZE = 4096;
endpackage
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/flash/include +incdir+../../sim/wb +incdir+../../sim/regs +incdir+../../sim"
files = [ "main.sv", "glbl.v", "SIM_CONFIG_S6_SERIAL.v", "../../sim/flash/M25P128.v" ]
modules = { "local" : [ "../../top/sfpga_bootloader" ] }
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vlog -sv main.sv +incdir+. +incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
vsim work.main -voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
run 30us
\ No newline at end of file
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
files = ["bicolor_led_ctrl_pkg.vhd",
"bicolor_led_ctrl.vhd",
"wb_addr_decoder.vhd",
"svec_afpga_top.vhd",
"csr.vhd",
"svec_v0_afpga.ucf"]
fetchto = "ip_cores"
modules = {
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ],
"svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl",
"http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl" ]
}
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