Skip to content

S
Simple VME FMC Carrier SVEC
Commit 7033fc15 authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

Add tester_wr design (board to test irq).

parent 56f5dc9f
Hide whitespace changes
Inline Side-by-side
Showing with 1147 additions and 0 deletions
hdl/syn/tester_wr/Manifest.py 0 → 100644
View file @ 7033fc15
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_project = "svec_tester_wr.xise"
syn_tool = "ise"
syn_top = "svec_tester_wr"
board = "svec"
ctrls = ["bank4_64b_32b"]
svec_base_ucf = ['wr', 'gpio', 'led']
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/tester_wr",
"../../syn/common",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/tester_wr/syn_extra_steps.tcl 0 → 100644
View file @ 7033fc15
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/top/tester_wr/Manifest.py 0 → 100644
View file @ 7033fc15
files = ["svec_tester_wr.vhd", "tester_wr_regs.vhd" ]
modules = {'local': ["../../rtl"]}
hdl/top/tester_wr/svec_tester_wr.vhd 0 → 100644
View file @ 7033fc15
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SVEC
-- https://ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: svec_tester_wr
--
-- description: SVEC carrier tester.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity svec_tester_wr is
generic (
-- WR PTP firmware.
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0;
-- Increase information messages during simulation
g_VERBOSE : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
rst_n_i : in std_logic;
-- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
-- 20MHz VCXO clock (for WR)
clk_20m_vcxo_i : in std_logic := '0';
-- 125 MHz GTP reference
clk_125m_gtp_n_i : in std_logic := '0';
clk_125m_gtp_p_i : in std_logic := '0';
---------------------------------------------------------------------------
-- VME interface
---------------------------------------------------------------------------
vme_write_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
vme_iackout_n_o : out std_logic;
vme_iackin_n_i : in std_logic;
vme_iack_n_i : in std_logic;
vme_gap_i : in std_logic;
vme_dtack_oe_o : out std_logic;
vme_dtack_n_o : out std_logic;
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_data_oe_n_o : out std_logic;
vme_data_dir_o : out std_logic;
vme_berr_o : out std_logic;
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic;
-- Presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
fmc1_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Carrier
---------------------------------------------------------------------------
-- Onewire interface
onewire_b : inout std_logic;
-- Carrier I2C eeprom
carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
pll25dac_din_o : out std_logic;
pll25dac_sclk_o : out std_logic;
pll25dac_sync_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '0';
sfp_mod_def0_i : in std_logic := '0'; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
------------------------------------------
-- DDR (bank 4 & 5)
------------------------------------------
ddr4_a_o : out std_logic_vector(13 downto 0);
ddr4_ba_o : out std_logic_vector(2 downto 0);
ddr4_cas_n_o : out std_logic;
ddr4_ck_n_o : out std_logic;
ddr4_ck_p_o : out std_logic;
ddr4_cke_o : out std_logic;
ddr4_dq_b : inout std_logic_vector(15 downto 0);
ddr4_ldm_o : out std_logic;
ddr4_ldqs_n_b : inout std_logic;
ddr4_ldqs_p_b : inout std_logic;
ddr4_odt_o : out std_logic;
ddr4_ras_n_o : out std_logic;
ddr4_reset_n_o : out std_logic;
ddr4_rzq_b : inout std_logic;
ddr4_udm_o : out std_logic;
ddr4_udqs_n_b : inout std_logic;
ddr4_udqs_p_b : inout std_logic;
ddr4_we_n_o : out std_logic;
-- PCB revision
pcbrev_i : in std_logic_vector(4 downto 0);
-- Carrier front panel LEDs
fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0);
-- GPIO
fp_gpio1_b : out std_logic; -- PPS output
fp_gpio2_b : out std_logic; -- not used
fp_gpio3_b : out std_logic; -- not used
fp_gpio4_b : out std_logic; -- not used
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
fp_gpio34_a2b_o : out std_logic
);
end entity svec_tester_wr;
architecture top of svec_tester_wr is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal app_wb_out : t_wishbone_master_out;
signal app_wb_in : t_wishbone_master_in;
-- Front panel LED control
signal led_state : std_logic_vector(15 downto 0);
signal wr_led_link : std_logic;
signal wr_led_act : std_logic;
signal wr_led_pps : std_logic;
signal tm_time_valid : std_logic;
signal tm_link_valid : std_logic;
signal vme_access : std_logic;
signal tm_tai : std_logic_vector (39 downto 0);
signal tm_cycles : std_logic_vector (27 downto 0);
signal pps_p : std_logic;
signal start_tai : std_logic_vector (31 downto 0);
signal start_cycles : std_logic_vector (31 downto 0);
signal period_cycles: std_logic_vector (31 downto 0);
signal total_count : std_logic_vector (31 downto 0);
signal current_count : std_logic_vector (31 downto 0);
signal current_cycles : std_logic_vector (31 downto 0);
signal ack_int : std_logic_vector (31 downto 0);
signal ack_int_wr : std_logic;
signal ack_count : std_logic_vector (31 downto 0);
signal irq : std_logic;
begin
inst_svec_base: entity work.svec_base_wr
generic map (
g_with_vic => True,
g_with_onewire => False,
g_with_spi => True,
g_with_wr => True,
g_with_ddr4 => False,
g_with_ddr5 => False,
g_app_offset => x"0000_0000",
g_num_user_irq => 1,
g_dpram_initf => g_dpram_initf,
g_fabric_iface => open,
g_streamers_op_mode => open,
g_tx_streamer_params => open,
g_rx_streamer_params => open,
g_simulation => g_SIMULATION,
g_verbose => g_VERBOSE
)
port map (
rst_n_i => rst_n_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
vme_write_n_i => vme_write_n_i,
vme_sysreset_n_i => vme_sysreset_n_i,
vme_retry_oe_o => vme_retry_oe_o,
vme_retry_n_o => vme_retry_n_o,
vme_lword_n_b => vme_lword_n_b,
vme_iackout_n_o => vme_iackout_n_o,
vme_iackin_n_i => vme_iackin_n_i,
vme_iack_n_i => vme_iack_n_i,
vme_gap_i => vme_gap_i,
vme_dtack_oe_o => vme_dtack_oe_o,
vme_dtack_n_o => vme_dtack_n_o,
vme_ds_n_i => vme_ds_n_i,
vme_data_oe_n_o => vme_data_oe_n_o,
vme_data_dir_o => vme_data_dir_o,
vme_berr_o => vme_berr_o,
vme_as_n_i => vme_as_n_i,
vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_addr_dir_o => vme_addr_dir_o,
vme_irq_o => vme_irq_o,
vme_ga_i => vme_ga_i,
vme_data_b => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_b => vme_addr_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc1_scl_b => fmc1_scl_b,
fmc1_sda_b => fmc1_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
fmc1_prsnt_m2c_n_i => fmc1_prsnt_m2c_n_i,
onewire_b => onewire_b,
carrier_scl_b => carrier_scl_b,
carrier_sda_b => carrier_sda_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr4_a_o => ddr4_a_o,
ddr4_ba_o => ddr4_ba_o,
ddr4_cas_n_o => ddr4_cas_n_o,
ddr4_ck_n_o => ddr4_ck_n_o,
ddr4_ck_p_o => ddr4_ck_p_o,
ddr4_cke_o => ddr4_cke_o,
ddr4_dq_b => ddr4_dq_b,
ddr4_ldm_o => ddr4_ldm_o,
ddr4_ldqs_n_b => ddr4_ldqs_n_b,
ddr4_ldqs_p_b => ddr4_ldqs_p_b,
ddr4_odt_o => ddr4_odt_o,
ddr4_ras_n_o => ddr4_ras_n_o,
ddr4_reset_n_o => ddr4_reset_n_o,
ddr4_rzq_b => ddr4_rzq_b,
ddr4_udm_o => ddr4_udm_o,
ddr4_udqs_n_b => ddr4_udqs_n_b,
ddr4_udqs_p_b => ddr4_udqs_p_b,
ddr4_we_n_o => ddr4_we_n_o,
ddr5_a_o => open,
ddr5_ba_o => open,
ddr5_cas_n_o => open,
ddr5_ck_n_o => open,
ddr5_ck_p_o => open,
ddr5_cke_o => open,
ddr5_dq_b => open,
ddr5_ldm_o => open,
ddr5_ldqs_n_b => open,
ddr5_ldqs_p_b => open,
ddr5_odt_o => open,
ddr5_ras_n_o => open,
ddr5_reset_n_o => open,
ddr5_rzq_b => open,
ddr5_udm_o => open,
ddr5_udqs_n_b => open,
ddr5_udqs_p_b => open,
ddr5_we_n_o => open,
pcbrev_i => pcbrev_i,
ddr4_clk_i => clk_sys_62m5,
ddr4_rst_n_i => rst_sys_62m5_n,
ddr4_wb_i.cyc => '0',
ddr4_wb_i.stb => '0',
ddr4_wb_i.adr => x"0000_0000",
ddr4_wb_i.sel => x"00",
ddr4_wb_i.we => '0',
ddr4_wb_i.dat => (63 downto 0 => '0'),
ddr4_wb_o => open,
ddr5_clk_i => clk_sys_62m5,
ddr5_rst_n_i => rst_sys_62m5_n,
ddr5_wb_i.cyc => '0',
ddr5_wb_i.stb => '0',
ddr5_wb_i.adr => x"0000_0000",
ddr5_wb_i.sel => x"00",
ddr5_wb_i.we => '0',
ddr5_wb_i.dat => (63 downto 0 => '0'),
ddr5_wb_o => open,
ddr4_wr_fifo_empty_o => open,
ddr5_wr_fifo_empty_o => open,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => open,
rst_ref_125m_n_o => open,
irq_user_i (6) => irq,
wrf_src_o => open,
wrf_src_i => open,
wrf_snk_o => open,
wrf_snk_i => open,
wrs_tx_data_i => open,
wrs_tx_valid_i => open,
wrs_tx_dreq_o => open,
wrs_tx_last_i => open,
wrs_tx_flush_i => open,
wrs_tx_cfg_i => open,
wrs_rx_first_o => open,
wrs_rx_last_o => open,
wrs_rx_data_o => open,
wrs_rx_valid_o => open,
wrs_rx_dreq_i => open,
wrs_rx_cfg_i => open,
wb_eth_master_o => open,
wb_eth_master_i => open,
tm_link_up_o => tm_link_valid,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => pps_p,
pps_led_o => wr_led_pps,
link_ok_o => open,
led_link_o => wr_led_link,
led_act_o => wr_led_act,
app_wb_o => app_wb_out,
app_wb_i => app_wb_in
);
------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
------------------------------------------------------------------------------
cmp_led_controller : entity work.gc_bicolor_led_ctrl
generic map(
g_nb_column => 4,
g_nb_line => 2,
g_clk_freq => 62500000, -- in Hz
g_refresh_rate => 250) -- in Hz
port map(
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
led_intensity_i => "1100100", -- in %
led_state_i => led_state,
column_o => fp_led_column_o,
line_o => fp_led_line_o,
line_oen_o => fp_led_line_oen_o);
cmp_vme_access_led : gc_extend_pulse
generic map (
g_width => 2500000)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => '0',
extended_o => vme_access);
-- LED order on front panel (top to bottom)
-- 7-6 5-4 3-2 1-0
-- 15-14 13-12 11-10 9-8
led_state(1 downto 0) <= c_led_off;
led_state(3 downto 2) <= c_led_off;
led_state(5 downto 4) <= c_led_green when wr_led_pps = '1' else c_led_off;
led_state(7 downto 6) <= c_led_green when wr_led_link = '1' else c_led_red;
led_state(9 downto 8) <= c_led_red_green when vme_access = '1' else c_led_off;
led_state(11 downto 10) <= c_led_off;
led_state(13 downto 12) <= c_led_green when tm_time_valid = '1' else c_led_red;
led_state(15 downto 14) <= c_led_red_green when wr_led_act = '1' else c_led_off;
-- Front panel IO configuration
fp_gpio1_b <= pps_p;
fp_gpio2_b <= '0';
fp_gpio3_b <= '0';
fp_gpio4_b <= '0';
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1';
fp_gpio34_a2b_o <= '1';
inst_regs: entity work.tester_wr_regs
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => app_wb_out,
wb_o => app_wb_in,
status_time_valid_i => tm_time_valid,
status_link_valid_i => tm_link_valid,
tm_tai_i (63 downto 40) => (others => '0'),
tm_tai_i (39 downto 0) => tm_tai,
tm_cycles_i (31 downto 28) => (others => '0'),
tm_cycles_i (27 downto 0) => tm_cycles,
start_tai_o => start_tai,
start_cycles_o => start_cycles,
period_cycles_o => period_cycles,
total_count_o => total_count,
current_count_i => current_count,
ack_int_o => ack_int,
ack_int_wr_o => ack_int_wr,
ack_count_i => ack_count
);
process (clk_sys_62m5) is
variable cur_cycles : std_logic_vector (31 downto 0);
variable en : std_logic;
begin
if rising_edge (clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ack_count <= (others => '0');
current_count <= (others => '0');
cur_cycles := (others => '0');
en := '0';
irq <= '0';
elsif tm_time_valid = '1' then
if start_tai = tm_tai (31 downto 0)
and start_cycles (27 downto 0) = tm_cycles
and total_count /= (31 downto 0 => '0')
then
-- Start interrupt generation.
current_count <= (others => '0');
ack_count <= (others => '0');
cur_cycles := (others => '0');
en := '1';
end if;
if en = '1' then
if cur_cycles = period_cycles then
-- Generate the irq.
irq <= '1';
cur_cycles := (others => '0');
current_count <= std_logic_vector (unsigned (current_count) + 1);
else
cur_cycles := std_logic_vector (unsigned (cur_cycles) + 1);
end if;
if current_count = total_count then
-- End of generation.
en := '0';
end if;
end if;
if ack_int_wr = '1' then
-- Ack interrupt.
irq <= '0';
if irq = '1' and ack_int = current_count then
ack_count <= std_logic_vector (unsigned (ack_count) + 1);
end if;
end if;
end if;
end if;
current_cycles <= cur_cycles;
end process;
end architecture top;
hdl/top/tester_wr/tester_wr_regs.cheby 0 → 100644
View file @ 7033fc15
memory-map:
bus: wb-32-be
name: tester_wr_regs
description: Memory map of the SVEC tester board
x-hdl:
busgroup: True
children:
- reg:
name: status
description: General status
address: 0x2008
width: 32
access: ro
children:
- field:
name: time_valid
description: Set when WR has time
range: 0
- field:
name: link_valid
description: Set when WR has link
range: 1
- reg:
name: tm_tai
description: TAI from wr
width: 64
access: ro
- reg:
name: tm_cycles
description: number of cycles (16Mhz) within the second
width: 32
access: ro
- reg:
name: start_tai
description: absolute TAI (LSB) for interrupts
width: 32
access: rw
- reg:
name: start_cycles
description: absolute cycles for interrupts
width: 32
access: rw
- reg:
name: period_cycles
description: number of cycles between interrupts
width: 32
access: rw
- reg:
name: total_count
description: number of interrupts to deliver
width: 32
access: rw
- reg:
name: current_count
description: number of interrupts delivered.
width: 32
access: ro
- reg:
name: ack_int
description: the current number of interrupts must be written to ack the interrupt.
width: 32
access: wo
x-hdl:
write-strobe: True
- reg:
name: ack_count
description: number of interrupts successfully ack-ed; cleared at the start
width: 32
access: ro
hdl/top/tester_wr/tester_wr_regs.h 0 → 100644
View file @ 7033fc15
#ifndef __CHEBY__TESTER_WR_REGS__H__
#define __CHEBY__TESTER_WR_REGS__H__
#define TESTER_WR_REGS_SIZE 8248
/* General status */
#define TESTER_WR_REGS_STATUS 0x2008UL
#define TESTER_WR_REGS_STATUS_TIME_VALID 0x1UL
#define TESTER_WR_REGS_STATUS_LINK_VALID 0x2UL
/* TAI from wr */
#define TESTER_WR_REGS_TM_TAI 0x2010UL
/* number of cycles (16Mhz) within the second */
#define TESTER_WR_REGS_TM_CYCLES 0x2018UL
/* absolute TAI (LSB) for interrupts */
#define TESTER_WR_REGS_START_TAI 0x201cUL
/* absolute cycles for interrupts */
#define TESTER_WR_REGS_START_CYCLES 0x2020UL
/* number of cycles between interrupts */
#define TESTER_WR_REGS_PERIOD_CYCLES 0x2024UL
/* number of interrupts to deliver */
#define TESTER_WR_REGS_TOTAL_COUNT 0x2028UL
/* number of interrupts delivered. */
#define TESTER_WR_REGS_CURRENT_COUNT 0x202cUL
/* the current number of interrupts must be written to ack the interrupt. */
#define TESTER_WR_REGS_ACK_INT 0x2030UL
/* number of interrupts successfully ack-ed; cleared at the start */
#define TESTER_WR_REGS_ACK_COUNT 0x2034UL
struct tester_wr_regs {
/* padding to: 2050 words */
uint32_t __padding_0[2050];
/* [0x2008]: REG (ro) General status */
uint32_t status;
/* padding to: 2052 words */
uint32_t __padding_1[1];
/* [0x2010]: REG (ro) TAI from wr */
uint64_t tm_tai;
/* [0x2018]: REG (ro) number of cycles (16Mhz) within the second */
uint32_t tm_cycles;
/* [0x201c]: REG (rw) absolute TAI (LSB) for interrupts */
uint32_t start_tai;
/* [0x2020]: REG (rw) absolute cycles for interrupts */
uint32_t start_cycles;
/* [0x2024]: REG (rw) number of cycles between interrupts */
uint32_t period_cycles;
/* [0x2028]: REG (rw) number of interrupts to deliver */
uint32_t total_count;
/* [0x202c]: REG (ro) number of interrupts delivered. */
uint32_t current_count;
/* [0x2030]: REG (wo) the current number of interrupts must be written to ack the interrupt. */
uint32_t ack_int;
/* [0x2034]: REG (ro) number of interrupts successfully ack-ed; cleared at the start */
uint32_t ack_count;
};
#endif /* __CHEBY__TESTER_WR_REGS__H__ */
hdl/top/tester_wr/tester_wr_regs.vhd 0 → 100644
View file @ 7033fc15
-- Do not edit. Generated on Mon Apr 06 15:32:18 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i tester_wr_regs.cheby --gen-hdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity tester_wr_regs is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- General status
-- Set when WR has time
status_time_valid_i : in std_logic;
-- Set when WR has time
status_link_valid_i : in std_logic;
-- TAI from wr
tm_tai_i : in std_logic_vector(63 downto 0);
-- number of cycles (16Mhz) within the second
tm_cycles_i : in std_logic_vector(31 downto 0);
-- absolute TAI (LSB) for interrupts
start_tai_o : out std_logic_vector(31 downto 0);
-- absolute cycles for interrupts
start_cycles_o : out std_logic_vector(31 downto 0);
-- number of cycles between interrupts
period_cycles_o : out std_logic_vector(31 downto 0);
-- number of interrupts to deliver
total_count_o : out std_logic_vector(31 downto 0);
-- number of interrupts delivered.
current_count_i : in std_logic_vector(31 downto 0);
-- the current number of interrupts must be written to ack the interrupt.
ack_int_o : out std_logic_vector(31 downto 0);
ack_int_wr_o : out std_logic;
-- number of interrupts successfully ack-ed; cleared at the start
ack_count_i : in std_logic_vector(31 downto 0)
);
end tester_wr_regs;
architecture syn of tester_wr_regs is
signal adr_int : std_logic_vector(13 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal start_tai_reg : std_logic_vector(31 downto 0);
signal start_tai_wreq : std_logic;
signal start_tai_wack : std_logic;
signal start_cycles_reg : std_logic_vector(31 downto 0);
signal start_cycles_wreq : std_logic;
signal start_cycles_wack : std_logic;
signal period_cycles_reg : std_logic_vector(31 downto 0);
signal period_cycles_wreq : std_logic;
signal period_cycles_wack : std_logic;
signal total_count_reg : std_logic_vector(31 downto 0);
signal total_count_wreq : std_logic;
signal total_count_wack : std_logic;
signal ack_int_reg : std_logic_vector(31 downto 0);
signal ack_int_wreq : std_logic;
signal ack_int_wack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(13 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(13 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Register status
-- Register tm_tai
-- Register tm_cycles
-- Register start_tai
start_tai_o <= start_tai_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
start_tai_reg <= "00000000000000000000000000000000";
start_tai_wack <= '0';
else
if start_tai_wreq = '1' then
start_tai_reg <= wr_dat_d0;
end if;
start_tai_wack <= start_tai_wreq;
end if;
end if;
end process;
-- Register start_cycles
start_cycles_o <= start_cycles_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
start_cycles_reg <= "00000000000000000000000000000000";
start_cycles_wack <= '0';
else
if start_cycles_wreq = '1' then
start_cycles_reg <= wr_dat_d0;
end if;
start_cycles_wack <= start_cycles_wreq;
end if;
end if;
end process;
-- Register period_cycles
period_cycles_o <= period_cycles_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
period_cycles_reg <= "00000000000000000000000000000000";
period_cycles_wack <= '0';
else
if period_cycles_wreq = '1' then
period_cycles_reg <= wr_dat_d0;
end if;
period_cycles_wack <= period_cycles_wreq;
end if;
end if;
end process;
-- Register total_count
total_count_o <= total_count_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
total_count_reg <= "00000000000000000000000000000000";
total_count_wack <= '0';
else
if total_count_wreq = '1' then
total_count_reg <= wr_dat_d0;
end if;
total_count_wack <= total_count_wreq;
end if;
end if;
end process;
-- Register current_count
-- Register ack_int
ack_int_o <= ack_int_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ack_int_reg <= "00000000000000000000000000000000";
ack_int_wack <= '0';
else
if ack_int_wreq = '1' then
ack_int_reg <= wr_dat_d0;
end if;
ack_int_wack <= ack_int_wreq;
end if;
end if;
end process;
ack_int_wr_o <= ack_int_wack;
-- Register ack_count
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, start_tai_wack, start_cycles_wack, period_cycles_wack, total_count_wack, ack_int_wack) begin
start_tai_wreq <= '0';
start_cycles_wreq <= '0';
period_cycles_wreq <= '0';
total_count_wreq <= '0';
ack_int_wreq <= '0';
case wr_adr_d0(13 downto 3) is
when "10000000001" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg status
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "10000000010" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg tm_tai
wr_ack_int <= wr_req_d0;
when "1" =>
-- Reg tm_tai
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "10000000011" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg tm_cycles
wr_ack_int <= wr_req_d0;
when "1" =>
-- Reg start_tai
start_tai_wreq <= wr_req_d0;
wr_ack_int <= start_tai_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "10000000100" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg start_cycles
start_cycles_wreq <= wr_req_d0;
wr_ack_int <= start_cycles_wack;
when "1" =>
-- Reg period_cycles
period_cycles_wreq <= wr_req_d0;
wr_ack_int <= period_cycles_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "10000000101" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg total_count
total_count_wreq <= wr_req_d0;
wr_ack_int <= total_count_wack;
when "1" =>
-- Reg current_count
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "10000000110" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg ack_int
ack_int_wreq <= wr_req_d0;
wr_ack_int <= ack_int_wack;
when "1" =>
-- Reg ack_count
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (adr_int, rd_req_int, status_time_valid_i, status_link_valid_i, tm_tai_i, tm_cycles_i, start_tai_reg, start_cycles_reg, period_cycles_reg, total_count_reg, current_count_i, ack_count_i) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
case adr_int(13 downto 3) is
when "10000000001" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg status
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= status_time_valid_i;
rd_dat_d0(1) <= status_link_valid_i;
rd_dat_d0(31 downto 2) <= (others => '0');
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "10000000010" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg tm_tai
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= tm_tai_i(63 downto 32);
when "1" =>
-- Reg tm_tai
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= tm_tai_i(31 downto 0);
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "10000000011" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg tm_cycles
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= tm_cycles_i;
when "1" =>
-- Reg start_tai
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= start_tai_reg;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "10000000100" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg start_cycles
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= start_cycles_reg;
when "1" =>
-- Reg period_cycles
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= period_cycles_reg;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "10000000101" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg total_count
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= total_count_reg;
when "1" =>
-- Reg current_count
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= current_count_i;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "10000000110" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg ack_int
rd_ack_d0 <= rd_req_int;
when "1" =>
-- Reg ack_count
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ack_count_i;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment