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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
56f5dc9f
Commit
56f5dc9f
authored
Apr 06, 2020
by
Tristan Gingold
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svec_base_wr: export decode_am generic.
parent
66d49b05
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5 deletions
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-5
svec_base_wr.vhd
hdl/rtl/svec_base_wr.vhd
+7
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hdl/rtl/svec_base_wr.vhd
View file @
56f5dc9f
...
...
@@ -42,6 +42,8 @@ use unisim.vcomponents.all;
entity
svec_base_wr
is
generic
(
-- For the VME64x interface: if true, also consider AM in the decoder.
g_DECODE_AM
:
boolean
:
=
TRUE
;
-- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
g_WITH_VIC
:
boolean
:
=
True
;
g_WITH_ONEWIRE
:
boolean
:
=
True
;
...
...
@@ -358,7 +360,7 @@ architecture top of svec_base_wr is
signal
csr_ddr4_data_wack
:
std_logic
;
signal
csr_ddr4_data_rack
:
std_logic
;
--
--
signal
ddr4_read_ip
:
std_logic
;
signal
ddr4_write_ip
:
std_logic
;
...
...
@@ -380,7 +382,7 @@ architecture top of svec_base_wr is
signal
vme_ga
:
std_logic_vector
(
5
downto
0
);
signal
vme_berr_n
:
std_logic
;
signal
vme_irq_n
:
std_logic_vector
(
7
downto
1
);
-- The wishbone bus to the carrier part.
signal
carrier_wb_out
:
t_wishbone_slave_out
;
signal
carrier_wb_in
:
t_wishbone_slave_in
;
...
...
@@ -463,7 +465,7 @@ begin -- architecture top
cmp_vme_core
:
entity
work
.
xvme64x_core
generic
map
(
g_CLOCK_PERIOD
=>
16
,
g_DECODE_AM
=>
TRUE
,
g_DECODE_AM
=>
g_DECODE_AM
,
g_USER_CSR_EXT
=>
FALSE
,
g_WB_GRANULARITY
=>
BYTE
,
g_WB_MODE
=>
PIPELINED
,
...
...
@@ -567,7 +569,7 @@ begin -- architecture top
csr_ddr4_addr_i
=>
csr_ddr4_addr
,
csr_ddr4_addr_o
=>
csr_ddr4_addr_out
,
csr_ddr4_addr_wr_o
=>
csr_ddr4_addr_wr
,
-- data to read or to write in ddr4
csr_ddr4_data_i
=>
csr_ddr4_data_in
,
csr_ddr4_data_o
=>
csr_ddr4_data_out
,
...
...
@@ -575,7 +577,7 @@ begin -- architecture top
csr_ddr4_data_rd_o
=>
csr_ddr4_data_rd
,
csr_ddr4_data_wack_i
=>
csr_ddr4_data_wack
,
csr_ddr4_data_rack_i
=>
csr_ddr4_data_rack
,
-- Thermometer and unique id
therm_id_i
=>
therm_id_in
,
therm_id_o
=>
therm_id_out
,
...
...
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