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Simple VME FMC Carrier SVEC
Commit 69ae6b68 authored by Tristan Gingold's avatar Tristan Gingold
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vmecore_test: add reload counter

parent e2f9aa8e
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Showing with 40 additions and 6 deletions
hdl/top/vmecore_test/vmecore_test.vhd
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...@@ -61,6 +61,8 @@ architecture rtl of vmecore_test is ...@@ -61,6 +61,8 @@ architecture rtl of vmecore_test is
-- 0x3000: pattern ram (0x1000 * 4B) -- 0x3000: pattern ram (0x1000 * 4B)
-- 0x4000 - 0x3ff000: pattern ram -- 0x4000 - 0x3ff000: pattern ram
signal counter : unsigned(31 downto 0); signal counter : unsigned(31 downto 0);
signal delay_counter : unsigned(31 downto 0);
signal reload_counter : unsigned(31 downto 0);
signal irq_status : std_logic; signal irq_status : std_logic;
signal leds : std_logic_vector(15 downto 0); signal leds : std_logic_vector(15 downto 0);
...@@ -101,6 +103,21 @@ begin ...@@ -101,6 +103,21 @@ begin
end if; end if;
end pattern_write; end pattern_write;
function write_reg(val : unsigned(31 downto 0);
sel : std_logic_vector(3 downto 0);
dat : std_logic_vector(31 downto 0)) return unsigned
is
variable res : unsigned(31 downto 0);
begin
res := val;
for i in 3 downto 0 loop
if sel (i) = '1' then
res(8*i + 7 downto 8*i) := unsigned(dat(8*i + 7 downto 8*i));
end if;
end loop;
return res;
end write_reg;
variable idx : natural; variable idx : natural;
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
...@@ -109,6 +126,8 @@ begin ...@@ -109,6 +126,8 @@ begin
if rst_n_i = '0' then if rst_n_i = '0' then
counter <= (others => '0'); counter <= (others => '0');
delay_counter <= (others => '0');
reload_counter <= (others => '0');
leds <= (others => '0'); leds <= (others => '0');
nbr_read <= (others => '0'); nbr_read <= (others => '0');
nbr_write <= (others => '0'); nbr_write <= (others => '0');
...@@ -123,6 +142,10 @@ begin ...@@ -123,6 +142,10 @@ begin
if counter = 1 then if counter = 1 then
int_o <= '1'; int_o <= '1';
irq_status <= '1'; irq_status <= '1';
if reload_counter /= 0 then
counter <= delay_counter;
reload_counter <= reload_counter - 1;
end if;
end if; end if;
end if; end if;
...@@ -172,12 +195,16 @@ begin ...@@ -172,12 +195,16 @@ begin
when "10" => when "10" =>
case slave_i.adr(2 downto 0) is case slave_i.adr(2 downto 0) is
when "000" => when "000" =>
for i in 3 downto 0 loop -- delay
if slave_i.sel (i) = '1' then counter <= write_reg (counter, slave_i.sel, slave_i.dat);
counter(8*i + 7 downto 8*i) <= when "001" =>
unsigned(slave_i.dat(8*i + 7 downto 8*i)); -- Interrupt status
end if; when "010" =>
end loop; -- reload delay
delay_counter <= write_reg (delay_counter, slave_i.sel, slave_i.dat);
when "011" =>
-- reload counter
reload_counter <= write_reg (reload_counter, slave_i.sel, slave_i.dat);
when others => when others =>
null; null;
end case; end case;
...@@ -221,10 +248,17 @@ begin ...@@ -221,10 +248,17 @@ begin
when "10" => when "10" =>
case slave_i.adr(2 downto 0) is case slave_i.adr(2 downto 0) is
when "000" => when "000" =>
-- counter
slave_o.dat <= std_logic_vector(counter); slave_o.dat <= std_logic_vector(counter);
when "001" => when "001" =>
slave_o.dat <= (0 => irq_status, others => '0'); slave_o.dat <= (0 => irq_status, others => '0');
irq_status <= '0'; irq_status <= '0';
when "010" =>
-- delay
slave_o.dat <= std_logic_vector(delay_counter);
when "011" =>
-- reload
slave_o.dat <= std_logic_vector(reload_counter);
when others => when others =>
slave_o.dat <= (others => '0'); slave_o.dat <= (others => '0');
end case; end case;
......
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