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S
Simple VME FMC Carrier SVEC
Commit 62d25bcd authored by Federico Vaga's avatar Federico Vaga
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tool: style fixes 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 504cd753
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Showing with 74 additions and 68 deletions
software/tools/vme-flasher/svec-flasher.c
View file @ 62d25bcd
......@@ -70,7 +70,7 @@ struct bitstream {
struct vme_mapping map;
void *vme_va;
void release_vme()
void release_vme(void)
{
vme_unmap(&map, 1);
}
......@@ -83,9 +83,10 @@ void init_vme(int slot)
map.sizel = 0x1000;
map.vme_addrl = slot * 0x80000 + BOOTLOADER_BASE;
if ((vme_va = vme_map(&map, 1)) == NULL) {
vme_va = vme_map(&map, 1);
if (!vme_va) {
fprintf(stderr, "Could not map VME CSR space at 0x%08x\n",
map.vme_addrl);
map.vme_addrl);
exit(1);
}
atexit(release_vme);
......@@ -101,11 +102,10 @@ static uint32_t csr_readl(uint32_t addr)
return ntohl(*(volatile uint32_t *)(vme_va + addr));
}
void enter_bootloader()
void enter_bootloader(void)
{
int i = 0;
const uint32_t boot_seq[8] =
{ 0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe, 0xba, 0xbe };
const uint32_t boot_seq[8] = {0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe, 0xba, 0xbe};
/* magic sequence: unlock bootloader mode, disable application FPGA */
for (i = 0; i < 8; i++)
......@@ -118,23 +118,24 @@ void enter_bootloader()
exit(-1);
}
int version = SXLDR_CSR_VERSION_R(csr_readl( SXLDR_REG_CSR ));
int version = SXLDR_CSR_VERSION_R(csr_readl(SXLDR_REG_CSR));
printf("Bootloader version: %d\n", version);
}
/* Tests the presence of the SPI master in the bootloader to check if we are running
version > 1 (v1 does not have the version ID register) */
int spi_test_presence()
int spi_test_presence(void)
{
csr_writel( SXLDR_FAR_XFER | SXLDR_FAR_DATA_W(0xff),
SXLDR_REG_FAR);
csr_writel(SXLDR_FAR_XFER | SXLDR_FAR_DATA_W(0xff),
SXLDR_REG_FAR);
usleep(100000);
usleep(100000);
uint32_t far = csr_readl(SXLDR_REG_FAR);
uint32_t far = csr_readl(SXLDR_REG_FAR);
/* transaction is not complete after so much time? no SPI... */
return (far & SXLDR_FAR_READY);
/* transaction is not complete after so much time? no SPI... */
return (far & SXLDR_FAR_READY);
}
void spi_cs(int cs)
......@@ -143,7 +144,7 @@ void spi_cs(int cs)
usleep(1);
}
uint8_t spi_read8()
uint8_t spi_read8(void)
{
uint32_t far;
csr_writel(SXLDR_FAR_XFER | SXLDR_FAR_DATA_W(0xff) | SXLDR_FAR_CS,
......@@ -165,7 +166,7 @@ void spi_write8(uint8_t data)
} while (!(far & SXLDR_FAR_READY));
}
uint32_t flash_read_id()
uint32_t flash_read_id(void)
{
uint32_t val = 0;
......@@ -185,14 +186,16 @@ uint32_t flash_read_id()
return val;
}
static void flash_wait_completion()
static void flash_wait_completion(void)
{
int not_done = 1;
while (not_done) {
uint8_t stat;
spi_cs(1);
spi_write8(FLASH_RDSR); /* Read Status register */
uint8_t stat = spi_read8();
stat = spi_read8();
not_done = (stat & 0x01);
spi_cs(0);
}
......@@ -209,16 +212,17 @@ void flash_erase_sector(uint32_t addr)
flash_wait_completion();
}
void flash_write_enable()
void flash_write_enable(void)
{
spi_cs(1);
spi_write8(FLASH_WREN);
spi_cs(0);
}
void flash_program_page(uint32_t addr, const uint8_t * data, int size)
void flash_program_page(uint32_t addr, const uint8_t *data, int size)
{
int i;
spi_cs(1);
spi_write8(FLASH_PP); /* Page Program */
spi_write8((addr >> 16) & 0x00ff); /* Address to start writing (MSB) */
......@@ -232,7 +236,8 @@ void flash_program_page(uint32_t addr, const uint8_t * data, int size)
flash_wait_completion();
}
int flash_program(uint32_t addr, const uint8_t * data, int size, uint32_t flash_id)
int flash_program(uint32_t addr, const uint8_t *data, int size,
uint32_t flash_id)
{
int n = 0;
int ret = 0;
......@@ -288,6 +293,7 @@ int flash_program(uint32_t addr, const uint8_t * data, int size, uint32_t flash_
fprintf(stderr, "\nVerification...\n");
for (n = 0, p = data; n < size; p++, n++) {
uint8_t d = spi_read8();
if (d != *p) {
fprintf(stderr,
"Verification failed at offset 0x%06x (is: 0x%02x, should be: 0x%02x)\n.",
......@@ -304,7 +310,7 @@ flash_program_exit:
}
static int program_flash(struct bitstream *bitstream,
bool fpga_bootloader_flash)
bool fpga_bootloader_flash)
{
int ret = 0;
......@@ -318,6 +324,7 @@ static int program_flash(struct bitstream *bitstream,
}
uint32_t flash_id = flash_read_id();
if ((flash_id != ID_M25P128) && (flash_id != ID_MT25QL128)) {
fprintf(stderr, "Flash memory ID invalid (0x%.8x). ", flash_id);
fprintf(stderr, "You are probably running an old version of the bootloader\n");
......@@ -328,17 +335,17 @@ static int program_flash(struct bitstream *bitstream,
printf("Flash ID: 0x%.7x, OK\n", flash_id);
if (fpga_bootloader_flash) {
char confirm[1024];
printf("\nWARNING! You're about to update the SVEC bootloader. \nIf this operation fails (due to incorrect bitstream or power loss), the card "
"can be only recovered through JTAG.\n\n");
printf("Type 'yes' to continue or Ctrl-C to exit the program: ");
fgets(confirm, 1024, stdin);
if (strncmp(confirm,"yes", 3)) {
printf("Bootloader update aborted.\n");
return -1;
}
ret = flash_program(0, bitstream->buf, bitstream->size, flash_id);
char confirm[1024];
printf("\nWARNING! You're about to update the SVEC bootloader. \nIf this operation fails (due to incorrect bitstream or power loss), the card can be only recovered through JTAG.\n\n");
printf("Type 'yes' to continue or Ctrl-C to exit the program: ");
fgets(confirm, 1024, stdin);
if (strncmp(confirm, "yes", 3)) {
printf("Bootloader update aborted.\n");
return -1;
}
ret = flash_program(0, bitstream->buf, bitstream->size, flash_id);
} else {
ret = flash_program(BOOTLOADER_SDB_BASE, sdb_header, sizeof(sdb_header), flash_id);
if (ret == 0)
......@@ -361,35 +368,34 @@ static int program_afpga(struct bitstream *bitstream)
printf("Booting the Application FPGA with bitstream %s.\n",
bitstream->path);
csr_writel(SXLDR_CSR_SWRST, SXLDR_REG_CSR);
csr_writel(SXLDR_CSR_START | SXLDR_CSR_MSBF, SXLDR_REG_CSR);
while (i < bitstream->size) {
if (! (csr_readl(SXLDR_REG_FIFO_CSR) & SXLDR_FIFO_CSR_FULL))
{
uint32_t word = *(uint32_t *) ( bitstream->buf + i );
size_t n = (bitstream->size - i > 4 ? 4 : bitstream->size - i);
csr_writel((n - 1) | ((n<4) ? SXLDR_FIFO_R0_XLAST : 0), SXLDR_REG_FIFO_R0);
csr_writel(htonl(word), SXLDR_REG_FIFO_R1);
i+=n;
csr_writel(SXLDR_CSR_SWRST, SXLDR_REG_CSR);
csr_writel(SXLDR_CSR_START | SXLDR_CSR_MSBF, SXLDR_REG_CSR);
while (i < bitstream->size) {
if (!(csr_readl(SXLDR_REG_FIFO_CSR) & SXLDR_FIFO_CSR_FULL)) {
uint32_t word = *(uint32_t *) (bitstream->buf + i);
size_t n = (bitstream->size - i > 4 ? 4 : bitstream->size - i);
csr_writel((n - 1) | ((n < 4) ? SXLDR_FIFO_R0_XLAST : 0), SXLDR_REG_FIFO_R0);
csr_writel(htonl(word), SXLDR_REG_FIFO_R1);
i += n;
}
}
while (1) {
}
while (1) {
uint32_t rval = csr_readl(SXLDR_REG_CSR);
if (rval & SXLDR_CSR_DONE) {
printf("Bitstream loaded, status: %s\n", (rval & SXLDR_CSR_ERROR ? "ERROR" : "OK"));
/* give the VME bus control to App FPGA */
csr_writel(SXLDR_CSR_EXIT, SXLDR_REG_CSR);
if ( rval & SXLDR_CSR_ERROR )
csr_writel(SXLDR_CSR_EXIT, SXLDR_REG_CSR);
if (rval & SXLDR_CSR_ERROR)
return -1;
return 0;
}
}
}
return 0;
return 0;
}
......@@ -452,18 +458,18 @@ int main(int argc, char *argv[])
while ((opt = getopt(argc, argv, "h?bf")) != -1) {
switch (opt) {
default:
case 'h':
case '?':
help(argv[0]);
exit(EXIT_SUCCESS);
break;
case 'b':
fpga_bootloader_flash = true;
break;
case 'f':
fpga_configure = true;
break;
default:
case 'h':
case '?':
help(argv[0]);
exit(EXIT_SUCCESS);
break;
case 'b':
fpga_bootloader_flash = true;
break;
case 'f':
fpga_configure = true;
break;
}
}
......@@ -494,11 +500,11 @@ int main(int argc, char *argv[])
enter_bootloader();
if (!fpga_configure)
err = program_flash(&bitstream, fpga_bootloader_flash);
err = program_flash(&bitstream, fpga_bootloader_flash);
else
err = program_afpga(&bitstream);
err = program_afpga(&bitstream);
bitstream_buffer_free(&bitstream);
bitstream_buffer_free(&bitstream);
exit(err ? EXIT_SUCCESS : EXIT_FAILURE);
}
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