100% routing done, still needs some tracks clean out and pouring the polygons

59ce0aa0 · Greg · Tristan Gingold · 0e2d562c · 59ce0aa0 · 59ce0aa0
Commit 59ce0aa0 authored Mar 25, 2012 by Greg Committed by Tristan Gingold Feb 03, 2021
4 changed files
--- a/circuit_board/SVEC/PCB-Layout/SVFC.pcbdoc
+++ b/circuit_board/SVEC/PCB-Layout/SVFC.pcbdoc
--- a/circuit_board/SVEC/SVEC.PrjPcb
+++ b/circuit_board/SVEC/SVEC.PrjPcb
--- a/circuit_board/SVEC/Schematics/AFPGA.SchDoc
+++ b/circuit_board/SVEC/Schematics/AFPGA.SchDoc
--- a/circuit_board/SVEC/Schematics/FMC_CONNECTORS.SchDoc
+++ b/circuit_board/SVEC/Schematics/FMC_CONNECTORS.SchDoc