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Simple VME FMC Carrier SVEC
Commits
53f00ec7
Commit
53f00ec7
authored
Sep 13, 2017
by
Dimitris Lampridis
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remove unused project files
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Manifest.py
hdl/rtl/bootloader/Manifest.py
+0
-1
spi_master.vhd
hdl/rtl/bootloader/spi_master.vhd
+0
-205
xvme64x_core.vhd
hdl/top/golden/xvme64x_core.vhd
+0
-159
No files found.
hdl/rtl/bootloader/Manifest.py
View file @
53f00ec7
files
=
[
"flash_boot.vhd"
,
"m25p_flash.vhd"
,
"mini_vme.vhd"
,
"spi_master.vhd"
,
"xilinx_loader.vhd"
,
"sxldr_wbgen2_pkg.vhd"
,
"svec_xloader_wb.vhd"
,
...
...
hdl/rtl/bootloader/spi_master.vhd
deleted
100644 → 0
View file @
4436fb5a
-----------------------------------------------------------------------------
-- Title : SPI Bus Master
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : spi_master.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-01-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Just a simple SPI master (bus-less).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
spi_master
is
generic
(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2
:
integer
:
=
2
;
-- number of data bits per transfer
g_num_data_bits
:
integer
:
=
2
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- state of the Chip select line (1 = CS active). External control
-- allows for multi-transfer commands (SPI master itself does not
-- control the state of spi_cs_n_o)
cs_i
:
in
std_logic
;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i
:
in
std_logic
;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i
:
in
std_logic
;
-- TX Data input
data_i
:
in
std_logic_vector
(
g_num_data_bits
-
1
downto
0
);
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o
:
out
std_logic
;
-- data read from selected slave, valid when ready_o == 1.
data_o
:
out
std_logic_vector
(
g_num_data_bits
-
1
downto
0
);
-- these are obvious
spi_cs_n_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
);
end
spi_master
;
architecture
behavioral
of
spi_master
is
signal
divider
:
unsigned
(
11
downto
0
);
signal
tick
:
std_logic
;
signal
sreg
:
std_logic_vector
(
g_num_data_bits
-1
downto
0
);
signal
rx_sreg
:
std_logic_vector
(
g_num_data_bits
-1
downto
0
);
type
t_state
is
(
IDLE
,
TX_CS
,
TX_DAT1
,
TX_DAT2
,
TX_SCK1
,
TX_SCK2
,
TX_CS2
,
TX_GAP
);
signal
state
:
t_state
;
signal
sclk
:
std_logic
;
signal
counter
:
unsigned
(
4
downto
0
);
begin
-- rtl
-- Simple clock divder. Produces a 'tick' signal which defines the timing for
-- the main state machine transitions.
p_divide_spi_clock
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
divider
<=
(
others
=>
'0'
);
else
if
(
start_i
=
'1'
or
tick
=
'1'
)
then
divider
<=
(
others
=>
'0'
);
else
divider
<=
divider
+
1
;
end
if
;
end
if
;
end
if
;
end
process
;
tick
<=
divider
(
g_div_ratio_log2
);
-- Main state machine. Executes SPI transfers
p_main_fsm
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
state
<=
IDLE
;
sclk
<=
'0'
;
sreg
<=
(
others
=>
'0'
);
rx_sreg
<=
(
others
=>
'0'
);
spi_mosi_o
<=
'0'
;
counter
<=
(
others
=>
'0'
);
else
case
state
is
-- Waits for start of transfer command
when
IDLE
=>
sclk
<=
'0'
;
counter
<=
(
others
=>
'0'
);
if
(
start_i
=
'1'
)
then
sreg
<=
data_i
;
state
<=
TX_CS
;
spi_mosi_o
<=
data_i
(
sreg
'high
);
end
if
;
-- Generates a gap between the externally asserted Chip Select and
-- the beginning of data transfer
when
TX_CS
=>
if
tick
=
'1'
then
state
<=
TX_DAT1
;
end
if
;
-- Outputs subsequent bits to MOSI line.
when
TX_DAT1
=>
if
(
tick
=
'1'
)
then
spi_mosi_o
<=
sreg
(
sreg
'high
);
sreg
<=
sreg
(
sreg
'high
-1
downto
0
)
&
'0'
;
state
<=
TX_SCK1
;
end
if
;
-- Flips the SCLK (active edge)
when
TX_SCK1
=>
if
(
tick
=
'1'
)
then
sclk
<=
not
sclk
;
counter
<=
counter
+
1
;
state
<=
TX_DAT2
;
end
if
;
-- Shifts in bits read from the slave
when
TX_DAT2
=>
if
(
tick
=
'1'
)
then
rx_sreg
<=
rx_sreg
(
rx_sreg
'high
-1
downto
0
)
&
spi_miso_i
;
state
<=
TX_SCK2
;
end
if
;
-- Flips the SCLK (inactive edge). Checks if all bits have been
-- transferred.
when
TX_SCK2
=>
if
(
tick
=
'1'
)
then
sclk
<=
not
sclk
;
if
(
counter
=
g_num_data_bits
)
then
state
<=
TX_CS2
;
else
state
<=
TX_DAT1
;
end
if
;
end
if
;
-- Generates a gap for de-assertoin of CS line
when
TX_CS2
=>
if
(
tick
=
'1'
)
then
state
<=
TX_GAP
;
data_o
<=
rx_sreg
;
end
if
;
when
TX_GAP
=>
if
(
tick
=
'1'
)
then
state
<=
IDLE
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
ready_o
<=
'1'
when
(
state
=
IDLE
and
start_i
=
'0'
)
else
'0'
;
-- SCLK polarity control
spi_sclk_o
<=
sclk
xor
cpol_i
;
spi_cs_n_o
<=
not
cs_i
;
end
behavioral
;
hdl/top/golden/xvme64x_core.vhd
deleted
100644 → 0
View file @
4436fb5a
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
WORK
.
wishbone_pkg
.
all
;
use
work
.
vme64x_pack
.
all
;
entity
xvme64x_core
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
VME_AS_n_i
:
in
std_logic
;
VME_RST_n_i
:
in
std_logic
;
VME_WRITE_n_i
:
in
std_logic
;
VME_AM_i
:
in
std_logic_vector
(
5
downto
0
);
VME_DS_n_i
:
in
std_logic_vector
(
1
downto
0
);
VME_GA_i
:
in
std_logic_vector
(
5
downto
0
);
VME_BERR_o
:
out
std_logic
;
VME_DTACK_n_o
:
out
std_logic
;
VME_RETRY_n_o
:
out
std_logic
;
VME_RETRY_OE_o
:
out
std_logic
;
VME_LWORD_n_b_i
:
in
std_logic
;
VME_LWORD_n_b_o
:
out
std_logic
;
VME_ADDR_b_i
:
in
std_logic_vector
(
31
downto
1
);
VME_ADDR_b_o
:
out
std_logic_vector
(
31
downto
1
);
VME_DATA_b_i
:
in
std_logic_vector
(
31
downto
0
);
VME_DATA_b_o
:
out
std_logic_vector
(
31
downto
0
);
VME_IRQ_n_o
:
out
std_logic_vector
(
6
downto
0
);
VME_IACKIN_n_i
:
in
std_logic
;
VME_IACK_n_i
:
in
std_logic
;
VME_IACKOUT_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
VME_DATA_DIR_o
:
out
std_logic
;
VME_DATA_OE_N_o
:
out
std_logic
;
VME_ADDR_DIR_o
:
out
std_logic
;
VME_ADDR_OE_N_o
:
out
std_logic
;
master_o
:
out
t_wishbone_master_out
;
master_i
:
in
t_wishbone_master_in
;
irq_i
:
in
std_logic
;
irq_ack_o
:
out
std_logic
);
end
xvme64x_core
;
architecture
wrapper
of
xvme64x_core
is
component
VME64xCore_Top
generic
(
g_wb_data_width
:
integer
:
=
32
;
g_wb_addr_width
:
integer
:
=
64
;
g_CRAM_SIZE
:
integer
:
=
1024
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
VME_AS_n_i
:
in
std_logic
;
VME_RST_n_i
:
in
std_logic
;
VME_WRITE_n_i
:
in
std_logic
;
VME_AM_i
:
in
std_logic_vector
(
5
downto
0
);
VME_DS_n_i
:
in
std_logic_vector
(
1
downto
0
);
VME_GA_i
:
in
std_logic_vector
(
5
downto
0
);
VME_BERR_o
:
out
std_logic
;
VME_DTACK_n_o
:
out
std_logic
;
VME_RETRY_n_o
:
out
std_logic
;
VME_LWORD_n_i
:
in
std_logic
;
VME_LWORD_n_o
:
out
std_logic
;
VME_ADDR_i
:
in
std_logic_vector
(
31
downto
1
);
VME_ADDR_o
:
out
std_logic_vector
(
31
downto
1
);
VME_DATA_i
:
in
std_logic_vector
(
31
downto
0
);
VME_DATA_o
:
out
std_logic_vector
(
31
downto
0
);
VME_IRQ_o
:
out
std_logic_vector
(
6
downto
0
);
VME_IACKIN_n_i
:
in
std_logic
;
VME_IACK_n_i
:
in
std_logic
;
VME_IACKOUT_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
VME_DATA_DIR_o
:
out
std_logic
;
VME_DATA_OE_N_o
:
out
std_logic
;
VME_ADDR_DIR_o
:
out
std_logic
;
VME_ADDR_OE_N_o
:
out
std_logic
;
VME_RETRY_OE_o
:
out
std_logic
;
DAT_i
:
in
std_logic_vector
(
g_wb_data_width
-
1
downto
0
);
DAT_o
:
out
std_logic_vector
(
g_wb_data_width
-
1
downto
0
);
ADR_o
:
out
std_logic_vector
(
g_wb_addr_width
-
1
downto
0
);
CYC_o
:
out
std_logic
;
ERR_i
:
in
std_logic
;
RTY_i
:
in
std_logic
;
SEL_o
:
out
std_logic_vector
(
f_div8
(
g_wb_addr_width
)
-
1
downto
0
);
STB_o
:
out
std_logic
;
ACK_i
:
in
std_logic
;
WE_o
:
out
std_logic
;
STALL_i
:
in
std_logic
;
INT_ack_o
:
out
std_logic
;
IRQ_i
:
in
std_logic
;
debug
:
out
std_logic_vector
(
7
downto
0
));
end
component
;
signal
dat_out
,
dat_in
:
std_logic_vector
(
31
downto
0
);
signal
adr_out
:
std_logic_vector
(
63
downto
0
);
begin
-- wrapper
U_Wrapped_VME
:
VME64xCore_Top
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
VME_AS_n_i
=>
VME_AS_n_i
,
VME_RST_n_i
=>
VME_RST_n_i
,
VME_WRITE_n_i
=>
VME_WRITE_n_i
,
VME_AM_i
=>
VME_AM_i
,
VME_DS_n_i
=>
VME_DS_n_i
,
VME_GA_i
=>
VME_GA_i
,
VME_BERR_o
=>
VME_BERR_o
,
VME_DTACK_n_o
=>
VME_DTACK_n_o
,
VME_RETRY_n_o
=>
VME_RETRY_n_o
,
VME_RETRY_OE_o
=>
VME_RETRY_OE_o
,
VME_LWORD_n_i
=>
VME_LWORD_n_b_i
,
VME_LWORD_n_o
=>
VME_LWORD_n_b_o
,
VME_ADDR_i
=>
VME_ADDR_b_i
,
VME_ADDR_o
=>
VME_ADDR_b_o
,
VME_DATA_i
=>
VME_DATA_b_i
,
VME_DATA_o
=>
VME_DATA_b_o
,
VME_IRQ_o
=>
VME_IRQ_n_o
,
VME_IACKIN_n_i
=>
VME_IACKIN_n_i
,
VME_IACK_n_i
=>
VME_IACK_n_i
,
VME_IACKOUT_n_o
=>
VME_IACKOUT_n_o
,
VME_DTACK_OE_o
=>
VME_DTACK_OE_o
,
VME_DATA_DIR_o
=>
VME_DATA_DIR_o
,
VME_DATA_OE_N_o
=>
VME_DATA_OE_N_o
,
VME_ADDR_DIR_o
=>
VME_ADDR_DIR_o
,
VME_ADDR_OE_N_o
=>
VME_ADDR_OE_N_o
,
DAT_i
=>
dat_in
,
DAT_o
=>
dat_out
,
ADR_o
=>
adr_out
,
CYC_o
=>
master_o
.
cyc
,
ERR_i
=>
master_i
.
err
,
RTY_i
=>
master_i
.
rty
,
SEL_o
=>
open
,
STB_o
=>
master_o
.
stb
,
ACK_i
=>
master_i
.
ack
,
WE_o
=>
master_o
.
we
,
STALL_i
=>
master_i
.
stall
,
IRQ_i
=>
irq_i
,
INT_ack_o
=>
irq_ack_o
);
master_o
.
dat
<=
dat_out
(
31
downto
0
);
master_o
.
sel
<=
(
others
=>
'1'
);
master_o
.
adr
<=
adr_out
(
29
downto
0
)
&
"00"
;
dat_in
<=
master_i
.
dat
;
-- VME_IRQ_n_o <= (others => '0');
end
wrapper
;
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