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Simple VME FMC Carrier SVEC
Commit 454b1dbb authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: delete sfpga_bootloader testbench 

It is not possible to run this anymore, among other things it depends on hdl/sim/flash/M25P128.v,
which in turns depends on a missing file (include/DevParam.h).

If we really need it we can try to restore it and revive it one day, but the SFPGA bootloader has
been stable for years as it is.
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hdl/testbench/sfpga_bootloader/Manifest.py deleted 100644 → 0
View file @ 3ed4b39c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/flash/include +incdir+../../sim/wb +incdir+../../sim/regs +incdir+../../sim"
files = [ "main.sv", "glbl.v", "SIM_CONFIG_S6_SERIAL.v", "../../sim/flash/M25P128.v" ]
modules = { "local" : [ "../../top/sfpga_bootloader" ] }
hdl/testbench/sfpga_bootloader/SIM_CONFIG_S6_SERIAL.v deleted 100644 → 0
View file @ 3ed4b39c
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Function Simulation Library Component
// / / Configuration Simulation Model
// /___/ /\ Filename : SIM_CONFIG_S6_SERIAL.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 03/22/09 - Initial version of serial configuration simulation model for
// Spartann6.
// 11/25/09 - Fix CRC (CR538766)
// 02/24/10 - Change Tprog to 500 ns (CR550552)
// 03/03/10 - set mode_sample_flag to 0 when mode pin set wrong (CR552316)
// End Revision
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module SIM_CONFIG_S6_SERIAL2 (
DONE,
CCLK,
DIN,
INITB,
M,
PROGB
);
inout DONE;
input CCLK;
input DIN;
inout INITB;
input [1:0] M;
input PROGB;
parameter DEVICE_ID = 32'h0;
localparam cfg_Tprog = 500000; // min PROG must be low, 300 ns
localparam cfg_Tpl = 100000; // max program latency us.
localparam STARTUP_PH0 = 3'b000;
localparam STARTUP_PH1 = 3'b001;
localparam STARTUP_PH2 = 3'b010;
localparam STARTUP_PH3 = 3'b011;
localparam STARTUP_PH4 = 3'b100;
localparam STARTUP_PH5 = 3'b101;
localparam STARTUP_PH6 = 3'b110;
localparam STARTUP_PH7 = 3'b111;
wire GSR, GTS, GWE;
wire cclk_in;
wire init_b_in;
wire prog_b_in;
wire crc_err_flag_tot;
reg crc_err_flag_reg = 0;
reg mode_sample_flag = 0;
reg init_b_p = 1;
reg done_o = 0;
tri1 p_up;
triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_p;
triand (weak1, strong0) DONE=done_o;
assign DONE = p_up;
assign INITB = p_up;
wire done_in;
reg por_b;
wire [1:0] m_in;
reg [2:0] mode_pin_in = 3'b0;
wire [15:0] d_in;
wire [15:0] d_out;
// assign glbl.GSR = GSR;
// assign glbl.GTS = GTS;
// assign glbl.GWE = GWE;
wire d_out_en;
wire init_b_t;
wire prog_b_t;
wire crc_rst;
buf buf_cclk (cclk_in, CCLK);
buf buf_din (ds_in, DIN);
// buf buf_dout (DOUT, ds_out);
buf buf_init (init_b_in, INITB);
buf buf_m_0 (m_in[0], M[0]);
buf buf_m_1 (m_in[1], M[1]);
buf buf_prog (prog_b_in, PROGB);
time prog_pulse_low_edge = 0;
time prog_pulse_low = 0;
integer wr_cnt = 0;
reg [4:0] csbo_cnt = 5'b0;
reg csbo_flag = 0;
reg dcm_locked = 1;
reg [4:0] conti_data_cnt = 5'b0;
reg [5:0] rd_data_cnt = 6'b0;
reg [15:0] pack_in_reg = 16'b0;
reg [5:0] reg_addr;
reg [5:0] rd_reg_addr;
reg new_data_in_flag = 0;
reg wr_flag = 1;
reg rd_flag = 0;
reg cmd_wr_flag = 0;
reg cmd_rd_flag = 0;
reg bus_sync_flag = 0;
reg [1:0] buswidth = 2'b00;
reg rd_sw_en = 0;
reg conti_data_flag = 0;
reg conti_data_flag_set = 0;
reg [2:0] st_state = STARTUP_PH0;
reg startup_begin_flag = 0;
reg startup_end_flag = 0;
reg cmd_reg_new_flag = 0;
reg far_maj_min_flag = 0;
reg crc_reset = 0;
reg crc_ck = 0;
reg crc_err_flag = 0;
wire crc_en, desync_flag;
reg [21:0] crc_curr = 22'b0;
reg [21:0] crc_new = 22'b0;
reg [21:0] crc_input = 22'b0;
reg gwe_out = 0;
reg gts_out = 1;
reg reboot_set = 0;
reg gsr_set = 0;
reg gts_usr_b = 1;
reg done_pin_drv = 0;
reg crc_bypass = 0;
reg reset_on_err = 0;
reg sync_timeout = 0;
reg [31:0] crc_reg, idcode_reg, idcode_tmp;
reg [15:0] far_maj_reg;
reg [15:0] far_min_reg;
reg [15:0] fdri_reg;
reg [15:0] fdro_reg;
reg [15:0] cwdt_reg;
reg [15:0] ctl_reg = 8'b10000001;
reg [4:0] cmd_reg;
reg [15:0] general1_reg;
reg [15:0] mask_reg = 8'b0;
reg [15:0] lout_reg, flr_reg;
reg [15:0] cor1_reg = 16'b0x11011100000000;
reg [15:0] cor2_reg = 16'b0000100111101110;
reg [15:0] pwrdn_reg = 16'bx00010001000x001;
reg [15:0] snowplow_reg;
reg [15:0] hc_opt_reg;
reg [15:0] csbo_reg;
reg [15:0] general2_reg;
reg [15:0] mode_reg;
reg [15:0] general3_reg;
reg [15:0] general4_reg;
reg [15:0] general5_reg;
reg [15:0] eye_mask_reg;
reg [15:0] cbc_reg;
reg [15:0] seu_reg;
reg [15:0] bootsts_reg;
reg [15:0] pu_gwe_reg;
reg [15:0] pu_gts_reg;
reg [15:0] mfwr_reg;
reg [15:0] cclk_freq_reg;
reg [15:0] seu_opt_reg;
reg [31:0] exp_sign_reg;
reg [15:0] rdbk_sign_reg;
reg shutdown_set = 0;
reg desynch_set = 0;
reg [2:0] done_cycle_reg = 3'b100;
reg [2:0] gts_cycle_reg = 3'b101;
reg [2:0] gwe_cycle_reg=3'b110;
reg [2:0] nx_st_state = 3'b000;
reg ghigh_b = 0;
reg eos_startup = 0;
reg startup_set = 0;
reg [1:0] startup_set_pulse = 2'b0;
reg [7:0] tmp_byte;
reg [7:0] tmp_byte1;
reg [7:0] tmp_byte2;
reg [7:0] tmp_byte3;
reg [7:0] tmp_byte4;
reg [7:0] tmp_byte5;
reg [7:0] tmp_byte6;
reg [7:0] tmp_byte7;
reg [15:0] tmp_word;
reg [7:0] ctl_reg_tmp;
reg id_error_flag = 0;
reg iprog_b = 1;
reg persist_en = 0;
reg rst_sync = 0;
reg [2:0] lock_cycle_reg = 3'b0;
reg rbcrc_no_pin = 0;
reg gsr_st_out = 1;
reg gsr_cmd_out = 0;
wire [15:0] stat_reg;
wire rst_intl;
wire rw_en;
wire gsr_out;
wire cfgerr_b_flag;
reg [27:0] downcont = 28'b0;
reg type2_flag = 0;
reg rst_en=1, prog_b_a=1;
reg [31:0] tmp_dword1;
reg [31:0] tmp_dword2;
integer wr_bit_addr;
initial begin
if (DEVICE_ID == 32'h0) begin
$display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_S6_SERIAL instance %m is not set.");
end
end
assign GSR = gsr_out;
assign GTS = gts_out;
assign GWE = gwe_out;
assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot;
assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg;
assign crc_en = 1;
assign done_in = DONE;
assign init_b_t = init_b_in;
always @( negedge prog_b_in) begin
rst_en = 0;
rst_en <= #cfg_Tprog 1;
end
always @( posedge rst_en or posedge prog_b_in )
if (rst_en == 1) begin
if (prog_b_in == 0 )
init_b_p <= 0;
else
init_b_p <= #(cfg_Tpl) 1;
end
always @( rst_en or prog_b_in or prog_pulse_low)
if (rst_en == 1) begin
if (prog_pulse_low == cfg_Tprog) begin
prog_b_a = 0;
prog_b_a <= #500 1;
end
else
prog_b_a = prog_b_in;
end
else
prog_b_a = 1;
initial begin
por_b = 0;
por_b = #400000 1;
end
assign prog_b_t = prog_b_a & iprog_b & por_b;
assign rst_intl = (prog_b_t == 0 ) ? 0 : 1;
always @( init_b_t or prog_b_t)
begin
$display("StupidP");
if (prog_b_t == 0)
mode_sample_flag <= 0;
else if (init_b_t && mode_sample_flag == 0) begin
if (prog_b_t == 1) begin
mode_pin_in <= m_in;
if (m_in != 2'b11) begin
mode_sample_flag <= 0;
$display("Error: input M is %h. Only Slave Serial mode M=11 supported on SIM_CONFIG_S6_SERIAL instance %m.", m_in);
end
else
mode_sample_flag <= #1 1;
end
end
end // always @ ( init_b_t or prog_b_t)
always @(posedge init_b_t )
if (prog_b_t != 1) begin
if ($time != 0 )
$display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time);
end
always @(m_in)
if (mode_sample_flag == 1 && persist_en == 1)
$display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time);
always @(posedge prog_b_in or negedge prog_b_in)
if (prog_b_in == 0)
prog_pulse_low_edge <= $time;
else if (prog_b_in == 1 && $time > 0) begin
prog_pulse_low = $time - prog_pulse_low_edge;
if (prog_pulse_low < cfg_Tprog )
$display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_S6_SERIAL instance %m at time %t.", cfg_Tprog, $time);
end
assign rw_en = (mode_sample_flag == 1 && done_o === 0) ? 1 : 0;
assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag;
always @(posedge cclk_in or posedge desync_flag)
if (desync_flag == 1) begin
pack_in_reg <= 16'b0;
new_data_in_flag <= 0;
bus_sync_flag <= 0;
wr_cnt <= 0;
wr_flag <= 1;
tmp_dword1 <= 32'b0;
tmp_dword2 <= 32'b0;
end
else begin
if (rw_en == 1 ) begin
if (bus_sync_flag == 0) begin
tmp_dword1 = { tmp_dword2[30:0], ds_in};
if (tmp_dword1[31:0] == 32'hAA995566) begin
bus_sync_flag <= 1;
new_data_in_flag <= 0;
tmp_dword2 <= 32'b0;
pack_in_reg <= 16'b0;
wr_cnt <= 0;
end
else begin
tmp_dword2 <= tmp_dword1;
end
end
else begin
pack_in_reg <= {pack_in_reg[14:0], ds_in};
if (wr_cnt == 15) begin
new_data_in_flag <= 1;
wr_cnt <= 0;
end
else begin
new_data_in_flag <= 0;
wr_cnt <= wr_cnt + 1;
end
end
end
else begin //rw_en = 0
new_data_in_flag <= 0;
end
end
always @(negedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
conti_data_flag <= 0;
conti_data_cnt <= 5'b0;
cmd_wr_flag <= 0;
cmd_rd_flag <= 0;
id_error_flag <= 0;
far_maj_min_flag <= 0;
cmd_reg_new_flag <= 0;
crc_curr <= 22'b0;
crc_ck <= 0;
csbo_cnt <= 0;
csbo_flag <= 0;
downcont <= 28'b0;
rd_data_cnt <= 0;
end
else begin
if (crc_reset == 1 ) begin
crc_reg <= 32'b0;
exp_sign_reg <= 32'b0;
crc_ck <= 0;
crc_curr <= 22'b0;
end
if (desynch_set == 1 || crc_err_flag==1) begin
conti_data_flag <= 0;
conti_data_cnt <= 5'b0;
cmd_wr_flag <= 0;
cmd_rd_flag <= 0;
far_maj_min_flag <= 0;
cmd_reg_new_flag <= 0;
crc_ck <= 0;
csbo_cnt <= 0;
csbo_flag <= 0;
downcont <= 28'b0;
rd_data_cnt <= 0;
end
if (new_data_in_flag == 1 && wr_flag == 1) begin
if (conti_data_flag == 1 ) begin
if (type2_flag == 0) begin
case (reg_addr)
6'b000000 : if (conti_data_cnt == 5'b00001) begin
crc_reg[15:0] <= pack_in_reg;
crc_ck <= 1;
end
else if (conti_data_cnt == 5'b00010) begin
crc_reg[31:16] <= pack_in_reg;
crc_ck <= 0;
end
6'b000001 : if (conti_data_cnt == 5'b00010) begin
far_maj_reg <= pack_in_reg;
far_maj_min_flag <=1;
end
else if (conti_data_cnt == 5'b00001) begin
if (far_maj_min_flag ==1) begin
far_min_reg <= pack_in_reg;
far_maj_min_flag <= 0;
end
else
far_maj_reg <= pack_in_reg;
end
6'b000010 : far_min_reg <= pack_in_reg;
6'b000011 : fdri_reg <= pack_in_reg;
6'b000101 : cmd_reg <= pack_in_reg[4:0];
6'b000110 : begin
ctl_reg_tmp = (pack_in_reg & ~mask_reg) | (ctl_reg & mask_reg);
ctl_reg <= {8'b0, ctl_reg_tmp[7:0]};
end
6'b000111 : mask_reg <= pack_in_reg;
6'b001001 : lout_reg <= pack_in_reg;
6'b001010 : cor1_reg <= pack_in_reg;
6'b001011 : cor2_reg <= pack_in_reg;
6'b001100 : pwrdn_reg <= pack_in_reg;
6'b001101 : flr_reg <= pack_in_reg;
6'b001110 :
if (conti_data_cnt == 5'b00001) begin
idcode_reg[15:0] <= pack_in_reg;
idcode_tmp = {idcode_reg[31:16], pack_in_reg};
$display("IDCode: %x", idcode_tmp);
if (idcode_tmp[27:0] != DEVICE_ID[27:0]) begin
id_error_flag <= 1;
$display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_S6_SERIAL instance %m at time %t.", idcode_tmp, DEVICE_ID, $time);
end
else
id_error_flag <= 0;
end
else if (conti_data_cnt == 5'b00010)
idcode_reg[31:16] <= pack_in_reg;
6'b001111 : cwdt_reg <= pack_in_reg;
6'b010000 : hc_opt_reg[6:0] <= pack_in_reg[6:0];
6'b010011 : general1_reg <= pack_in_reg;
6'b010100 : general2_reg <= pack_in_reg;
6'b010101 : general3_reg <= pack_in_reg;
6'b010110 : general4_reg <= pack_in_reg;
6'b010111 : general5_reg <= pack_in_reg;
6'b011000 : mode_reg <= pack_in_reg;
6'b011001 : pu_gwe_reg <= pack_in_reg;
6'b011010 : pu_gts_reg <= pack_in_reg;
6'b011011 : mfwr_reg <= pack_in_reg;
6'b011100 : cclk_freq_reg <= pack_in_reg;
6'b011101 : seu_opt_reg <= pack_in_reg;
6'b011110 : if (conti_data_cnt == 5'b00001)
exp_sign_reg[15:0] <= pack_in_reg;
else if (conti_data_cnt == 5'b00010)
exp_sign_reg[31:16] <= pack_in_reg;
6'b011111 : if (conti_data_cnt == 5'b00001)
rdbk_sign_reg[15:0] <= pack_in_reg;
else if (conti_data_cnt == 5'b00010)
rdbk_sign_reg[31:16] <= pack_in_reg;
6'b100001 : eye_mask_reg <= pack_in_reg;
6'b100010 : cbc_reg <= pack_in_reg;
endcase
if (reg_addr == 6'b000101)
cmd_reg_new_flag <= 1;
else
cmd_reg_new_flag <= 0;
if (crc_en == 1) begin
if (reg_addr == 6'h05 && pack_in_reg[4:0] == 5'b00111)
crc_curr[21:0] = 22'b0;
else begin
if (reg_addr != 6'h04 && reg_addr != 6'h08 && reg_addr != 6'h09 &&
reg_addr != 6'h12 && reg_addr != 6'h1f &&
reg_addr != 6'h20 && reg_addr != 6'h00) begin
crc_input[21:0] = {reg_addr[5:0], pack_in_reg};
crc_new[21:0] = crc_next(crc_curr, crc_input);
crc_curr[21:0] <= crc_new;
end
end
end
end
else begin // type2_flag
if (conti_data_cnt == 2)
downcont[27:16] <= pack_in_reg[11:0];
else if (conti_data_cnt ==1)
downcont[15:0] <= pack_in_reg;
end
if (conti_data_cnt <= 5'b00001) begin
conti_data_cnt <= 5'b0;
type2_flag <= 0;
end
else
conti_data_cnt <= conti_data_cnt - 1;
end
else begin //if (conti_data_flag == 0 )
if ( downcont >= 1) begin
if (crc_en == 1) begin
crc_input[21:0] = {6'b000011, pack_in_reg}; //FDRI address plus data
crc_new[21:0] = crc_next(crc_curr, crc_input);
crc_curr[21:0] <= crc_new;
end
end
if (pack_in_reg[15:13] == 3'b010 && downcont == 0 ) begin
// $display("Warning : only Type 1 Packet supported on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time);
cmd_wr_flag <= 0;
type2_flag <= 1;
conti_data_flag <= 1;
conti_data_cnt <= 5'b00010;
end
else if (pack_in_reg[15:13] == 3'b001 ) begin
if (pack_in_reg[12:11] == 2'b01 && downcont == 0) begin
if (pack_in_reg[4:0] != 5'b0) begin
cmd_rd_flag <= 1;
cmd_wr_flag <= 0;
// rd_data_cnt <= {pack_in_reg[4:0], 1'b0};
rd_data_cnt <= 6'b000100;
conti_data_cnt <= 5'b0;
conti_data_flag = 0;
rd_reg_addr <= pack_in_reg[10:5];
end
end
else if (pack_in_reg[12:11] == 2'b10 && downcont == 0) begin
if (pack_in_reg[15:5] == 11'b00110010010) begin // csbo reg
csbo_reg <= pack_in_reg;
csbo_cnt = pack_in_reg[4:0];
csbo_flag <= 1;
conti_data_flag = 0;
reg_addr <= pack_in_reg[10:5];
cmd_wr_flag <= 1;
conti_data_cnt <= 5'b0;
end
else if (pack_in_reg[4:0] != 5'b0 ) begin
cmd_wr_flag <= 1;
conti_data_flag <= 1;
conti_data_cnt <= pack_in_reg[4:0];
reg_addr <= pack_in_reg[10:5];
end
end
else begin
cmd_wr_flag <= 0;
conti_data_flag <= 0;
conti_data_cnt <= 5'b0;
end
end
cmd_reg_new_flag <= 0;
crc_ck <= 0;
end // if (conti_data_flag == 0 )
if (csbo_cnt != 0 ) begin
if (csbo_flag)
csbo_cnt <= csbo_cnt - 1;
end
else
csbo_flag <= 0;
if (conti_data_cnt == 5'b00001 )
conti_data_flag <= 0;
end
if (rw_en == 1) begin
if (rd_data_cnt == 1) begin
rd_data_cnt <= 0;
end
else if (rd_data_cnt == 0 && rd_flag == 1)
cmd_rd_flag <= 0;
else if (cmd_rd_flag == 1 && rd_flag == 1)
rd_data_cnt <= rd_data_cnt - 1;
if (downcont >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1)
downcont <= downcont - 1;
end
if (crc_ck == 1)
crc_ck <= 0;
end
assign crc_rst = crc_reset | ~rst_intl;
always @(posedge cclk_in or posedge crc_rst )
if (crc_rst == 1)
crc_err_flag <= 0;
else
if (crc_ck == 1) begin
if (crc_bypass == 1) begin
if (crc_reg[31:0] != 32'h9876defc)
crc_err_flag <= 1;
else
crc_err_flag <= 0;
end
else begin
if (crc_curr[21:0] != crc_reg[21:0])
crc_err_flag <= 1;
else
crc_err_flag <= 0;
end
end
else
crc_err_flag <= 0;
always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag)
if (rst_intl == 0)
crc_err_flag_reg <= 0;
else if (crc_err_flag == 1)
crc_err_flag_reg <= 1;
else
crc_err_flag_reg <= 0;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
startup_set <= 0;
crc_reset <= 0;
gsr_set <= 0;
shutdown_set <= 0;
desynch_set <= 0;
reboot_set <= 0;
ghigh_b <= 0;
end
else begin
if (cmd_reg_new_flag == 1) begin
if (cmd_reg == 5'b00011)
ghigh_b <= 1;
else if (cmd_reg == 5'b01000)
ghigh_b <= 0;
if (cmd_reg == 5'b00101)
startup_set <= 1;
if (cmd_reg == 5'b00111)
crc_reset <= 1;
if (cmd_reg == 5'b01010)
gsr_set <= 1;
if (cmd_reg == 5'b01011)
shutdown_set <= 1;
if (cmd_reg == 5'b01101)
desynch_set <= 1;
if (cmd_reg == 5'b01110)
reboot_set <= 1;
end
else begin
startup_set <= 0;
crc_reset <= 0;
gsr_set <= 0;
shutdown_set <= 0;
desynch_set <= 0;
reboot_set <= 0;
end
end
always @(posedge startup_set or posedge desynch_set or negedge rw_en )
if (rw_en == 0)
startup_set_pulse <= 2'b0;
else begin
if (startup_set_pulse == 2'b00 && startup_set ==1)
startup_set_pulse <= 2'b01;
else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin
startup_set_pulse <= 2'b11;
@(posedge cclk_in )
startup_set_pulse <= 2'b00;
end
end
always @(ctl_reg) begin
if (ctl_reg[3] == 1)
persist_en = 1;
else
persist_en = 0;
if (ctl_reg[0] == 1)
gts_usr_b = 1;
else
gts_usr_b = 0;
end
always @(cor1_reg)
begin
if (cor1_reg[2] ==1)
done_pin_drv = 1;
else
done_pin_drv = 0;
if (cor1_reg[4] == 1)
crc_bypass = 1;
else
crc_bypass = 0;
end
always @(cor2_reg) begin
if (cor2_reg[15] ==1)
reset_on_err = 1;
else
reset_on_err = 0;
done_cycle_reg = cor2_reg[11:9];
lock_cycle_reg = cor2_reg[8:6];
gts_cycle_reg = cor2_reg[5:3];
gwe_cycle_reg = cor2_reg[2:0];
end
assign stat_reg[15] = sync_timeout;
assign stat_reg[14] = 0;
assign stat_reg[13] = DONE;
assign stat_reg[12] = INITB;
assign stat_reg[11:9] = {1'b0, mode_pin_in};
assign stat_reg[8:6] = 3'b0;
assign stat_reg[5] = ghigh_b;
assign stat_reg[4] = gwe_out;
assign stat_reg[3] = gts_out;
assign stat_reg[2] = 1'bx;
assign stat_reg[1] = id_error_flag;
assign stat_reg[0] = crc_err_flag_reg;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
st_state <= STARTUP_PH0;
startup_begin_flag <= 0;
startup_end_flag <= 0;
end
else begin
if (nx_st_state == STARTUP_PH1) begin
startup_begin_flag <= 1;
startup_end_flag <= 0;
end
else if (st_state == STARTUP_PH7) begin
startup_end_flag <= 1;
startup_begin_flag <= 0;
end
if (lock_cycle_reg == 3'b111 || dcm_locked == 1 || st_state != lock_cycle_reg) begin
st_state <= nx_st_state;
end
else
st_state <= st_state;
end
always @(st_state or startup_set_pulse or DONE )
if (( st_state == done_cycle_reg) && (DONE != 0) || ( st_state != done_cycle_reg))begin
$display("NextState?");
case (st_state)
STARTUP_PH0 : if (startup_set_pulse == 2'b11 )
nx_st_state = STARTUP_PH1;
else
nx_st_state = STARTUP_PH0;
STARTUP_PH1 : nx_st_state = STARTUP_PH2;
STARTUP_PH2 : nx_st_state = STARTUP_PH3;
STARTUP_PH3 : nx_st_state = STARTUP_PH4;
STARTUP_PH4 : nx_st_state = STARTUP_PH5;
STARTUP_PH5 : nx_st_state = STARTUP_PH6;
STARTUP_PH6 : nx_st_state = STARTUP_PH7;
STARTUP_PH7 : nx_st_state = STARTUP_PH0;
endcase // case (st_state)
end // if (( st_state == done_cycle_reg) && (DONE != 0) || ( st_state != done_cycle_reg))
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0) begin
gwe_out <= 0;
gts_out <= 1;
eos_startup <= 0;
gsr_st_out <= 1;
done_o <= 0;
end
else begin
if ((nx_st_state == done_cycle_reg) || (st_state == done_cycle_reg))
if (DONE != 0 || done_pin_drv == 1)
done_o <= 1'b1;
else
done_o <= 1'bz;
if (nx_st_state == gwe_cycle_reg) begin
gwe_out <= 1;
end
if (nx_st_state == gts_cycle_reg) begin
gts_out <= 0;
end
if (nx_st_state == STARTUP_PH6)
gsr_st_out <= 0;
if (nx_st_state == STARTUP_PH7)
eos_startup <= 1;
end
assign gsr_out = gsr_st_out | gsr_cmd_out;
function [21:0] crc_next;
input [21:0] crc_curr;
input [21:0] crc_input;
integer i_crc;
begin
for(i_crc = 21; i_crc > 15; i_crc=i_crc -1)
crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc];
crc_next[15] = crc_curr[14] ^ crc_input[15] ^ crc_curr[21];
for(i_crc = 14; i_crc > 12; i_crc=i_crc -1)
crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc];
crc_next[12] = crc_curr[11] ^ crc_input[12] ^ crc_curr[21];
for(i_crc = 11; i_crc > 7; i_crc=i_crc -1)
crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc];
crc_next[7] = crc_curr[6] ^ crc_input[7] ^ crc_curr[21];
for(i_crc = 6; i_crc > 0; i_crc=i_crc -1)
crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc];
crc_next[0] = crc_input[0] ^ crc_curr[21];
end
endfunction
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
endmodule
hdl/testbench/sfpga_bootloader/glbl.v deleted 100644 → 0
View file @ 3ed4b39c
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
hdl/testbench/sfpga_bootloader/main.sv deleted 100644 → 0
View file @ 3ed4b39c
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "regs/sxldr_regs.vh"
`define WIRE_VME_PINS2(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_RST_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga(slot_id)),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_i(VME_BBSY_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
module main;
reg rst_n = 0;
reg clk_20m = 0;
wire cclk, din, program_b, init_b, done, suspend;
wire [1:0] m;
always #25ns clk_20m <= ~clk_20m;
initial begin
repeat(20000) @(posedge clk_20m);
rst_n = 1;
end
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave);
svec_sfpga_top
DUT (
.lclk_n_i(clk_20m),
.rst_n_i(rst_n),
`WIRE_VME_PINS2(8),
.boot_clk_o(cclk),
.boot_config_o(program_b),
.boot_status_i(init_b),
.boot_done_i(done),
.boot_dout_o(din),
.spi_cs_n_o(spi_cs),
.spi_sclk_o(spi_sclk),
.spi_mosi_o(spi_mosi),
.spi_miso_i(spi_miso)
);
SIM_CONFIG_S6_SERIAL2
#(
.DEVICE_ID(32'h34000093) // 6slx150t
) U_serial_sim
(
.DONE(done),
.CCLK(cclk),
.DIN(din),
.INITB(init_b),
.M(2'b11),
.PROGB(program_b)
);
M25Pxxx Flash(.S(spi_cs), .C(spi_sclk), .HOLD(1'b1), .D(spi_mosi), .Q(spi_miso), .Vpp_W(32'h0), .Vcc(32'd3000));
parameter [128*8:1] mem = "../../../software/sdb-flash/image.vmf";
defparam Flash.memory_file = mem;
class CSimDrv_Xloader;
protected CBusAccessor_VME64x acc;
protected uint64_t base;
protected byte _dummy;
function new(CBusAccessor_VME64x _acc, uint64_t _base);
acc = _acc;
base = _base;
endfunction
protected task flash_xfer(bit cs, byte data_in, ref byte data_out = _dummy);
uint64_t rv;
while(1) begin
acc.read(base + `ADDR_SXLDR_FAR, rv);
if(rv & `SXLDR_FAR_READY)
break;
end
acc.write(base + `ADDR_SXLDR_FAR, data_in | (cs ? `SXLDR_FAR_CS:0) | `SXLDR_FAR_XFER);
while(1) begin
acc.read(base + `ADDR_SXLDR_FAR, rv);
if(rv & `SXLDR_FAR_READY)
break;
end
data_out = rv & 'hff;
endtask // flash_xfer
task flash_command(int cmd, byte data_in[], output byte data_out[], input int size);
int i;
flash_xfer(0, 0);
flash_xfer(1, cmd);
for(i=0;i<size;i++)
begin
byte t;
flash_xfer(1, data_in[i], t);
data_out[i] = t;
end
flash_xfer(0, 0);
endtask // flash_command
task enter_boot_mode();
int i;
const int boot_seq[8] = '{'hde, 'had, 'hbe, 'hef, 'hca, 'hfe, 'hba, 'hbe};
for(i=0;i<8;i++)
acc.write(base + `ADDR_SXLDR_BTRIGR, boot_seq[i]);
endtask // enter_boot_mode
task exit_boot_mode();
acc.write(base + `ADDR_SXLDR_CSR, `SXLDR_CSR_EXIT);
endtask // enter_boot_mode
task load_bitstream(string filename);
int f,i, pos=0;
uint64_t csr;
acc.write(base + `ADDR_SXLDR_CSR, `SXLDR_CSR_SWRST );
acc.write(base + `ADDR_SXLDR_CSR, `SXLDR_CSR_START | `SXLDR_CSR_MSBF);
f = $fopen(filename, "r");
while(!$feof(f))
begin
uint64_t r,r2;
acc.read(base + `ADDR_SXLDR_FIFO_CSR, r);
if(!(r&`SXLDR_FIFO_CSR_FULL)) begin
int n;
int x;
n = $fread(x, f);
pos+=n;
if((pos % 4000) == 0)
$display("%d bytes sent", pos);
r=x;
r2=(n - 1) | ($feof(f) ? `SXLDR_FIFO_R0_XLAST : 0);
acc.write(base +`ADDR_SXLDR_FIFO_R0, r2);
acc.write(base +`ADDR_SXLDR_FIFO_R1, r);
end
end
$fclose(f);
while(1) begin
acc.read (base + `ADDR_SXLDR_CSR, csr);
if(csr & `SXLDR_CSR_DONE) begin
$display("Bitstream loaded, status: %s", (csr & `SXLDR_CSR_ERROR ? "ERROR" : "OK"));
acc.write(base + `ADDR_SXLDR_CSR, `SXLDR_CSR_EXIT);
return;
end
end
endtask
endclass
initial begin
uint64_t d;
byte payload[];
int i, result;
CBusAccessor_VME64x acc = new(VME.master);
CSimDrv_Xloader drv;
payload[0] = 0;
payload[1] = 0;
payload[2] = 0;
#1100us;
acc.set_default_modifiers(A32 | CR_CSR | D32);
drv = new(acc, 'h70000);
#100us;
drv.enter_boot_mode();
#100us;
// read ID from the flash
drv.flash_command('h9f, payload, payload, 3);
$display("Flash ID: %02x %02x %02x\n", payload[0], payload[1], payload[2]);
drv.exit_boot_mode();
// drv.load_bitstream("sample_bitstream/crc_gen.bin");
end
endmodule // main
hdl/testbench/sfpga_bootloader/run.do deleted 100644 → 0
View file @ 3ed4b39c
vlog -sv main.sv +incdir+. +incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
vsim work.main -voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
run 30us
\ No newline at end of file
hdl/testbench/sfpga_bootloader/wave.do deleted 100644 → 0
View file @ 3ed4b39c
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/clk_sys_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_vme_n_a_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_local_n_a_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_n_o
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/powerup_cnt
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/local_synced_n
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/vme_synced_n
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/powerup_n
add wave -noupdate /main/DUT/lclk_n_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/VME_AS_n_i
add wave -noupdate /main/DUT/VME_RST_n_i
add wave -noupdate /main/DUT/VME_WRITE_n_i
add wave -noupdate /main/DUT/VME_AM_i
add wave -noupdate /main/DUT/VME_DS_n_i
add wave -noupdate /main/DUT/VME_GA_i
add wave -noupdate /main/DUT/VME_DTACK_n_o
add wave -noupdate /main/DUT/VME_LWORD_n_b
add wave -noupdate /main/DUT/VME_ADDR_b
add wave -noupdate /main/DUT/VME_DATA_b
add wave -noupdate /main/DUT/VME_DTACK_OE_o
add wave -noupdate /main/DUT/VME_DATA_DIR_o
add wave -noupdate /main/DUT/VME_DATA_OE_N_o
add wave -noupdate /main/DUT/VME_ADDR_DIR_o
add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate /main/DUT/VME_BBSY_n_i
add wave -noupdate /main/DUT/boot_clk_o
add wave -noupdate /main/DUT/boot_config_o
add wave -noupdate /main/DUT/boot_done_i
add wave -noupdate /main/DUT/boot_dout_o
add wave -noupdate /main/DUT/boot_status_i
add wave -noupdate /main/DUT/spi_cs_n_o
add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/spi_sclk_o
add wave -noupdate /main/DUT/debugled_o
add wave -noupdate /main/DUT/pll_ce_o
add wave -noupdate /main/DUT/VME_DATA_o_int
add wave -noupdate /main/DUT/vme_dtack_oe_int
add wave -noupdate /main/DUT/VME_DTACK_n_int
add wave -noupdate /main/DUT/vme_data_dir_int
add wave -noupdate /main/DUT/VME_DATA_OE_N_int
add wave -noupdate /main/DUT/wb_vme_in
add wave -noupdate /main/DUT/wb_vme_out
add wave -noupdate /main/DUT/passive
add wave -noupdate /main/DUT/boot_en
add wave -noupdate /main/DUT/boot_trig_p1
add wave -noupdate /main/DUT/boot_exit_p1
add wave -noupdate /main/DUT/CONTROL
add wave -noupdate /main/DUT/CLK
add wave -noupdate /main/DUT/TRIG0
add wave -noupdate /main/DUT/TRIG1
add wave -noupdate /main/DUT/TRIG2
add wave -noupdate /main/DUT/TRIG3
add wave -noupdate /main/DUT/boot_config_int
add wave -noupdate /main/DUT/erase_afpga_n
add wave -noupdate /main/DUT/erase_afpga_n_d0
add wave -noupdate /main/DUT/pllout_clk_fb_sys
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/go_passive
add wave -noupdate /main/DUT/vme_idle
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2145098 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {17655808 ps}
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