Skip to content

S
Simple VME FMC Carrier SVEC
Commit 454b1dbb authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

hdl: delete sfpga_bootloader testbench 

It is not possible to run this anymore, among other things it depends on hdl/sim/flash/M25P128.v,
which in turns depends on a missing file (include/DevParam.h).

If we really need it we can try to restore it and revive it one day, but the SFPGA bootloader has
been stable for years as it is.
parent 3ed4b39c
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 0 additions and 1249 deletions
hdl/testbench/sfpga_bootloader/Manifest.py deleted 100644 → 0
View file @ 3ed4b39c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/flash/include +incdir+../../sim/wb +incdir+../../sim/regs +incdir+../../sim"
files = [ "main.sv", "glbl.v", "SIM_CONFIG_S6_SERIAL.v", "../../sim/flash/M25P128.v" ]
modules = { "local" : [ "../../top/sfpga_bootloader" ] }
hdl/testbench/sfpga_bootloader/SIM_CONFIG_S6_SERIAL.v deleted 100644 → 0
View file @ 3ed4b39c
This diff is collapsed.
hdl/testbench/sfpga_bootloader/glbl.v deleted 100644 → 0
View file @ 3ed4b39c
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
hdl/testbench/sfpga_bootloader/main.sv deleted 100644 → 0
View file @ 3ed4b39c
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "regs/sxldr_regs.vh"
`define WIRE_VME_PINS2(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_RST_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga(slot_id)),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_i(VME_BBSY_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
module main;
reg rst_n = 0;
reg clk_20m = 0;
wire cclk, din, program_b, init_b, done, suspend;
wire [1:0] m;
always #25ns clk_20m <= ~clk_20m;
initial begin
repeat(20000) @(posedge clk_20m);
rst_n = 1;
end
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave);
svec_sfpga_top
DUT (
.lclk_n_i(clk_20m),
.rst_n_i(rst_n),
`WIRE_VME_PINS2(8),
.boot_clk_o(cclk),
.boot_config_o(program_b),
.boot_status_i(init_b),
.boot_done_i(done),
.boot_dout_o(din),
.spi_cs_n_o(spi_cs),
.spi_sclk_o(spi_sclk),
.spi_mosi_o(spi_mosi),
.spi_miso_i(spi_miso)
);
SIM_CONFIG_S6_SERIAL2
#(
.DEVICE_ID(32'h34000093) // 6slx150t
) U_serial_sim
(
.DONE(done),
.CCLK(cclk),
.DIN(din),
.INITB(init_b),
.M(2'b11),
.PROGB(program_b)
);
M25Pxxx Flash(.S(spi_cs), .C(spi_sclk), .HOLD(1'b1), .D(spi_mosi), .Q(spi_miso), .Vpp_W(32'h0), .Vcc(32'd3000));
parameter [128*8:1] mem = "../../../software/sdb-flash/image.vmf";
defparam Flash.memory_file = mem;
class CSimDrv_Xloader;
protected CBusAccessor_VME64x acc;
protected uint64_t base;
protected byte _dummy;
function new(CBusAccessor_VME64x _acc, uint64_t _base);
acc = _acc;
base = _base;
endfunction
protected task flash_xfer(bit cs, byte data_in, ref byte data_out = _dummy);
uint64_t rv;
while(1) begin
acc.read(base + `ADDR_SXLDR_FAR, rv);
if(rv & `SXLDR_FAR_READY)
break;
end
acc.write(base + `ADDR_SXLDR_FAR, data_in | (cs ? `SXLDR_FAR_CS:0) | `SXLDR_FAR_XFER);
while(1) begin
acc.read(base + `ADDR_SXLDR_FAR, rv);
if(rv & `SXLDR_FAR_READY)
break;
end
data_out = rv & 'hff;
endtask // flash_xfer
task flash_command(int cmd, byte data_in[], output byte data_out[], input int size);
int i;
flash_xfer(0, 0);
flash_xfer(1, cmd);
for(i=0;i<size;i++)
begin
byte t;
flash_xfer(1, data_in[i], t);
data_out[i] = t;
end
flash_xfer(0, 0);
endtask // flash_command
task enter_boot_mode();
int i;
const int boot_seq[8] = '{'hde, 'had, 'hbe, 'hef, 'hca, 'hfe, 'hba, 'hbe};
for(i=0;i<8;i++)
acc.write(base + `ADDR_SXLDR_BTRIGR, boot_seq[i]);
endtask // enter_boot_mode
task exit_boot_mode();
acc.write(base + `ADDR_SXLDR_CSR, `SXLDR_CSR_EXIT);
endtask // enter_boot_mode
task load_bitstream(string filename);
int f,i, pos=0;
uint64_t csr;
acc.write(base + `ADDR_SXLDR_CSR, `SXLDR_CSR_SWRST );
acc.write(base + `ADDR_SXLDR_CSR, `SXLDR_CSR_START | `SXLDR_CSR_MSBF);
f = $fopen(filename, "r");
while(!$feof(f))
begin
uint64_t r,r2;
acc.read(base + `ADDR_SXLDR_FIFO_CSR, r);
if(!(r&`SXLDR_FIFO_CSR_FULL)) begin
int n;
int x;
n = $fread(x, f);
pos+=n;
if((pos % 4000) == 0)
$display("%d bytes sent", pos);
r=x;
r2=(n - 1) | ($feof(f) ? `SXLDR_FIFO_R0_XLAST : 0);
acc.write(base +`ADDR_SXLDR_FIFO_R0, r2);
acc.write(base +`ADDR_SXLDR_FIFO_R1, r);
end
end
$fclose(f);
while(1) begin
acc.read (base + `ADDR_SXLDR_CSR, csr);
if(csr & `SXLDR_CSR_DONE) begin
$display("Bitstream loaded, status: %s", (csr & `SXLDR_CSR_ERROR ? "ERROR" : "OK"));
acc.write(base + `ADDR_SXLDR_CSR, `SXLDR_CSR_EXIT);
return;
end
end
endtask
endclass
initial begin
uint64_t d;
byte payload[];
int i, result;
CBusAccessor_VME64x acc = new(VME.master);
CSimDrv_Xloader drv;
payload[0] = 0;
payload[1] = 0;
payload[2] = 0;
#1100us;
acc.set_default_modifiers(A32 | CR_CSR | D32);
drv = new(acc, 'h70000);
#100us;
drv.enter_boot_mode();
#100us;
// read ID from the flash
drv.flash_command('h9f, payload, payload, 3);
$display("Flash ID: %02x %02x %02x\n", payload[0], payload[1], payload[2]);
drv.exit_boot_mode();
// drv.load_bitstream("sample_bitstream/crc_gen.bin");
end
endmodule // main
hdl/testbench/sfpga_bootloader/run.do deleted 100644 → 0
View file @ 3ed4b39c
vlog -sv main.sv +incdir+. +incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
vsim work.main -voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
run 30us
\ No newline at end of file
hdl/testbench/sfpga_bootloader/wave.do deleted 100644 → 0
View file @ 3ed4b39c
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/clk_sys_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_vme_n_a_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_local_n_a_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_n_o
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/powerup_cnt
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/local_synced_n
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/vme_synced_n
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/powerup_n
add wave -noupdate /main/DUT/lclk_n_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/VME_AS_n_i
add wave -noupdate /main/DUT/VME_RST_n_i
add wave -noupdate /main/DUT/VME_WRITE_n_i
add wave -noupdate /main/DUT/VME_AM_i
add wave -noupdate /main/DUT/VME_DS_n_i
add wave -noupdate /main/DUT/VME_GA_i
add wave -noupdate /main/DUT/VME_DTACK_n_o
add wave -noupdate /main/DUT/VME_LWORD_n_b
add wave -noupdate /main/DUT/VME_ADDR_b
add wave -noupdate /main/DUT/VME_DATA_b
add wave -noupdate /main/DUT/VME_DTACK_OE_o
add wave -noupdate /main/DUT/VME_DATA_DIR_o
add wave -noupdate /main/DUT/VME_DATA_OE_N_o
add wave -noupdate /main/DUT/VME_ADDR_DIR_o
add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate /main/DUT/VME_BBSY_n_i
add wave -noupdate /main/DUT/boot_clk_o
add wave -noupdate /main/DUT/boot_config_o
add wave -noupdate /main/DUT/boot_done_i
add wave -noupdate /main/DUT/boot_dout_o
add wave -noupdate /main/DUT/boot_status_i
add wave -noupdate /main/DUT/spi_cs_n_o
add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/spi_sclk_o
add wave -noupdate /main/DUT/debugled_o
add wave -noupdate /main/DUT/pll_ce_o
add wave -noupdate /main/DUT/VME_DATA_o_int
add wave -noupdate /main/DUT/vme_dtack_oe_int
add wave -noupdate /main/DUT/VME_DTACK_n_int
add wave -noupdate /main/DUT/vme_data_dir_int
add wave -noupdate /main/DUT/VME_DATA_OE_N_int
add wave -noupdate /main/DUT/wb_vme_in
add wave -noupdate /main/DUT/wb_vme_out
add wave -noupdate /main/DUT/passive
add wave -noupdate /main/DUT/boot_en
add wave -noupdate /main/DUT/boot_trig_p1
add wave -noupdate /main/DUT/boot_exit_p1
add wave -noupdate /main/DUT/CONTROL
add wave -noupdate /main/DUT/CLK
add wave -noupdate /main/DUT/TRIG0
add wave -noupdate /main/DUT/TRIG1
add wave -noupdate /main/DUT/TRIG2
add wave -noupdate /main/DUT/TRIG3
add wave -noupdate /main/DUT/boot_config_int
add wave -noupdate /main/DUT/erase_afpga_n
add wave -noupdate /main/DUT/erase_afpga_n_d0
add wave -noupdate /main/DUT/pllout_clk_fb_sys
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/go_passive
add wave -noupdate /main/DUT/vme_idle
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2145098 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {17655808 ps}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment