• Dimitris Lampridis's avatar
    hdl: re-enable all timing constraints · febae170
    Dimitris Lampridis authored
    Some constraints were commented-out by Tristan because the golden
    did not use them and Xilinx ISE was producing errors because of that.
    
    This commits re-enables all constraints and enables an option in the Translate step of the golden
    design to demote empty timegroups to warnings instead.
    febae170
svec_base_common.ucf 8.13 KB