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Simple VME FMC Carrier SVEC
Commit febae170 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: re-enable all timing constraints 

Some constraints were commented-out by Tristan because the golden
did not use them and Xilinx ISE was producing errors because of that.

This commits re-enables all constraints and enables an option in the Translate step of the golden
design to demote empty timegroups to warnings instead.
parent feb22d89
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Showing with 12 additions and 9 deletions
hdl/syn/common/svec_base_common.ucf
View file @ febae170
......@@ -227,22 +227,22 @@ NET "*/gc_reset_async_in" TIG;
NET "inst_svec_base/clk_sys_62m5" TNM_NET = sys_clk;
NET "inst_svec_base/clk_ref_125m" TNM_NET = ref_clk;
TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
#TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
#TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
#TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
#TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
#TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
hdl/syn/golden/syn_extra_steps.tcl
View file @ febae170
......@@ -27,6 +27,9 @@ xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
# Needed because some timegroup constraints are too generic and do not exist in the golden
xilinx::project set "Allow Unmatched Timing Group Constraints" TRUE
xilinx::project save
xilinx::project close
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