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SPEC7
Commit f56230d9 authored by Peter Jansweijer's avatar Peter Jansweijer
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Merge branch 'proposed_master' 

re-point wr-cores to proposed_spec7
SHA-1: 54245d3ced79a8f3d04c4d0ca240b925cd74ae78
parents 5f9904e9 b34cbd82
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.gitignore 0 → 100644
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*.log
*.bit
*.jou
hdl/spec7_write_design/syn/work/
hdl/arm_base_system/syn/.gitignore 0 → 100644
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/.Xil
/NONE
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
hdl/arm_base_system/syn/README.TXT 0 → 100644
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Synthesis and Place&Route README.TXT October 09, 2019
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_vivado_prog.cmd download the configuration ("%DesName%.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
hdl/arm_base_system/syn/do_vivado.cmd 0 → 100644
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rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source viv_do_all.tcl
hdl/arm_base_system/syn/proj_file_list.txt 0 → 100644
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# From directory ../../wr-cores/syn/spec7_write_design
# hdlmake list-files > proj_file_list.txt
#../top/ip/processing_system7_0/processing_system7_0.xci
../top/arm_base_sys.vhd
../top/arm_base_sys.xdc
# include hardware version ID un FPGA USER_ID register:
hdl_version.xdc
hdl/arm_base_system/syn/proj_properties.tcl 0 → 100644
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#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
set proj_name arm_base_sys
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics ""
}
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
hdl/arm_base_system/syn/viv_do_all.tcl 0 → 100644
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# viv_do_all.tcl PeterJ, 24-Jan-2018.
#
# This script does:
# set project name
# set part name
# creates a new project
# imports the source files
# launches synthesis
# launches implementation
# generates a bitfile
# ------------------------------------
# set proj_name and proj_dir:
source proj_properties.tcl
# Format the raw time [clock seconds] to a date string
puts "[set date_string [clock format [clock seconds] -format "date: %y-%m-%d, time: %H:%M:%S"]] Implementation Started of $proj_name"
#Close currently open project and create a new one. (OVERWRITES PROJECT!!)
close_project -quiet
# Remove old and Create the new build directory
file delete -force $proj_dir
#file mkdir $proj_dir
create_project -force -part $device $proj_name ./$proj_dir
# work_directory is *full* path project directory.
# Vivado doesn't seem to accept relative paths!?
set work_directory [get_property DIRECTORY [current_project]]
# Create a hdl_version.xdc file to set the bitfile USERID to the revision date/version
set revision_log_file "revisiondate_log.txt"
if [file exists $revision_log_file] {
set revision_log_fileptr [open $revision_log_file]
gets $revision_log_fileptr revision_log_date
gets $revision_log_fileptr revision_log_revnumber
close $revision_log_fileptr
set userid [format "0x%6d%02d" $revision_log_date $revision_log_revnumber]
puts "Bitfile USERID set to $userid"
} else {
set userid 0xFFFFFFFF
puts "WARNING Bitfile USERID set to 0xFFFFFFFF"
}
set hdl_version_file [open hdl_version.xdc w]
puts $hdl_version_file "set_property BITSTREAM.CONFIG.USERID $userid \[current_design\]"
close $hdl_version_file
set_property target_language VHDL [current_project]
# ------------------------------------------------------------------------------
# Read source files
# ------------------------------------------------------------------------------
set fp [open "proj_file_list.txt" r]
set file_data [read $fp]
close $fp
set content [split $file_data "\n"]
set use_bmm false
foreach line $content {
puts $line
set line_length [ string length $line ]
if {[string range $line 0 0] == "#"} {
# puts "comment"
} elseif {[string range $line $line_length-4 $line_length] == ".vhd"} {
# puts "vhdl"
read_vhdl -library work $line
} elseif {[string range $line $line_length-2 $line_length] == ".v"} {
# puts "verilog"
read_verilog -library work $line
} elseif {[string range $line $line_length-3 $line_length] == ".vh"} {
# puts "verilog"
read_verilog -library work $line
} elseif {[string range $line $line_length-3 $line_length] == ".sv"} {
# puts "verilog"
read_verilog -sv -library work $line
} elseif {[string range $line $line_length-4 $line_length] == ".svh"} {
# puts "verilog"
read_verilog -sv -library work $line
} elseif {[string range $line $line_length-4 $line_length] == ".xci"} {
# puts "system verilog"
read_ip $line
} elseif {[string range $line $line_length-4 $line_length] == ".xdc"} {
# Read constraints file if any
# puts "xdc"
read_xdc -verbose $line
} elseif {[string range $line $line_length-4 $line_length] == ".bmm"} {
# Set pointer to bmm file if any
# puts "bmm"
set use_bmm true
set bmm_file [pwd]/$line
set bmm_bd ${proj_name}_bd.bmm
add_files -norecurse $bmm_file
}
}
# Set Top level
set_property top $proj_name [current_fileset]
set_property source_mgmt_mode All [current_project]
update_compile_order -fileset sources_1
# Pass generics
set_property generic $generics [current_fileset]
puts "INFO: Reading Source Files Done!"
source ../top/ip/processing_system_bd.tcl
# ------------------------------------------------------------------------------
source $script_dir/viv_do_synt.tcl
source $script_dir/viv_do_impl.tcl
if {$use_bmm} {
source $script_dir/viv_generate_bd_bmm.tcl
}
file copy -force $proj_dir/$proj_name.runs/impl_1/$proj_name.bit .
write_hw_platform -fixed -force -include_bit -file $proj_name.xsa
hdl/arm_base_system/top/arm_base_sys.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : WRPC reference design for SPEC7
-- : based on ZYNQ Z030/Z035/Z045
-- Project : ARM_BASE_SYS
-- URL : http://empir.npl.co.uk/write/
-------------------------------------------------------------------------------
-- File : arm_base_sys.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2019-10-09
-- Last update: 2019-10-09
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC7
-- in combination with the High Stability external Oscillator.
-- See also EMPIR 17IND14 WRITE Project (http://empir.npl.co.uk/write/)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
library unisim;
use unisim.vcomponents.all;
entity arm_base_sys is
port (
MIO : INOUT STD_LOGIC_VECTOR(53 DOWNTO 0);
DDR_CAS_n : INOUT STD_LOGIC;
DDR_CKE : INOUT STD_LOGIC;
DDR_Clk_n : INOUT STD_LOGIC;
DDR_Clk_p : INOUT STD_LOGIC;
DDR_CS_n : INOUT STD_LOGIC;
DDR_DRSTB : INOUT STD_LOGIC;
DDR_ODT : INOUT STD_LOGIC;
DDR_RAS_n : INOUT STD_LOGIC;
DDR_WEB : INOUT STD_LOGIC;
DDR_BankAddr : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
DDR_Addr : INOUT STD_LOGIC_VECTOR(14 DOWNTO 0);
DDR_VRN : INOUT STD_LOGIC;
DDR_VRP : INOUT STD_LOGIC;
DDR_DM : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DDR_DQS_n : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQS_p : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
PS_SRSTB : INOUT STD_LOGIC;
PS_CLK : INOUT STD_LOGIC;
PS_PORB : INOUT STD_LOGIC;
leds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end entity arm_base_sys;
architecture top of arm_base_sys is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
component processing_system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
gpio_rtl_0_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component processing_system;
begin
processing_system_i: component processing_system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_Clk_n,
DDR_ck_p => DDR_Clk_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_DRSTB,
DDR_we_n => DDR_WEB,
FIXED_IO_ddr_vrn => DDR_VRN,
FIXED_IO_ddr_vrp => DDR_VRP,
FIXED_IO_mio(53 downto 0) => MIO(53 downto 0),
FIXED_IO_ps_clk => PS_CLK,
FIXED_IO_ps_porb => PS_PORB,
FIXED_IO_ps_srstb => PS_SRSTB,
gpio_rtl_0_tri_o => leds(3 downto 0)
);
end architecture top;
hdl/arm_base_system/top/arm_base_sys.xdc 0 → 100644
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hdl/arm_base_system/top/ip/processing_system_bd.tcl 0 → 100644
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hdl/spec7_blink/sim/.gitignore 0 → 100644
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/spec7.lib
/*.bram
/*.mem
/*.bak
/*.wlf
/*.vstf
/*.lnk
/transcript
\ No newline at end of file
hdl/spec7_blink/sim/VCom_Functional.tcl 0 → 100644
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# VCom_Functional.tcl
# compile for functional simulation
vcom -explicit -93 -work work ../top/spec7_blink.vhd
hdl/spec7_blink/sim/VSim_Functional.tcl 0 → 100644
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vsim -t ns -G/spec7_blink/Q=4 work.spec7_blink
do wave.tcl
do testje.tcl
wave zoomfull
hdl/spec7_test/sim/modelsim.ini → hdl/spec7_blink/sim/modelsim.ini
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......@@ -14,7 +14,7 @@ INIVersion = "10.6b"
others=$VHDLLIBS/v10.6/modelsim_ise14_5.ini
work = spec7.lib
work = spec7_blink.lib
[DefineOptionset]
; Define optionset entries for the various compilers, vmake, and vsim.
; These option sets can be used with the "-optionset <optionsetname>" syntax.
......
hdl/spec7_blink/sim/testje.tcl 0 → 100644
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force CLK_DMTD_P 0,1 4000 ps -rep 8 ns
force CLK_DMTD_N 1,0 4000 ps -rep 8 ns
run 4 us
#run 200 ms
hdl/spec7_blink/sim/wave.tcl 0 → 100644
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /spec7_blink/CLK_DMTD_P
add wave -noupdate /spec7_blink/Q
add wave -noupdate -expand /spec7_blink/LED
add wave -noupdate /spec7_blink/u3_O
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1114 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {4200 ns}
hdl/spec7_blink/syn/.gitignore 0 → 100644
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/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
hdl/spec7_blink/syn/do_vivado_prog.cmd 0 → 100644
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rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
hdl/spec7_blink/syn/do_vivado_tcl.cmd 0 → 100644
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rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
hdl/spec7_blink/syn/proj_file_list.txt 0 → 100644
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../top/spec7_blink.vhd
spec7_blink.xdc
hdl/spec7_blink/syn/proj_properties.tcl 0 → 100644
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#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
set proj_name spec7_blink
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set generics ""
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
#set device xc7z035fbg676-1
set device xc7z030fbg676-1
hdl/spec7_blink/syn/spec7_blink.xdc 0 → 100644
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##### REFERENCE CLOCK #####
# CLK_DMTD input pins (on board 124.992 MHz Xtal)
# Note that 125.000 MHz is routed via AD9516!
set_property PACKAGE_PIN D15 [get_ports CLK_DMTD_P]
set_property IOSTANDARD LVDS [get_ports CLK_DMTD_P]
set_property PACKAGE_PIN D14 [get_ports CLK_DMTD_N]
set_property IOSTANDARD LVDS [get_ports CLK_DMTD_N]
create_clock -period 8.000 -name CLK_DMTD_P [get_ports CLK_DMTD_P]
# LED_0 to 3
set_property IOSTANDARD LVCMOS25 [get_ports {LED[0]}]
set_property PACKAGE_PIN AC26 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {LED[1]}]
set_property PACKAGE_PIN AB26 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {LED[2]}]
set_property PACKAGE_PIN AE26 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {LED[3]}]
set_property PACKAGE_PIN AE25 [get_ports {LED[3]}]
# Suicide & Watchdog
# Bank 13 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AC22 [get_ports suicide_n_o]
set_property IOSTANDARD LVCMOS25 [get_ports suicide_n_o]
set_property PACKAGE_PIN AC21 [get_ports wdog_n_o]
set_property IOSTANDARD LVCMOS25 [get_ports wdog_n_o]
set_property PACKAGE_PIN V19 [get_ports prsnt_m2c_l_i]
set_property IOSTANDARD LVCMOS25 [get_ports prsnt_m2c_l_i]
hdl/spec7_blink/top/spec7_blink.vhd 0 → 100644
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--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 8.3 Revision 5 from HDL Works B.V.
--
-- Ease library : design
-- HDL library : work
-- Host name : SERING
-- User name : peterj
-- Time stamp : Tue Nov 26 16:59:52 2019
--
-- Designed by :
-- Company :
-- Project info :
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Object : Entity design.KnightRider
-- Last modified : Thu Nov 14 16:30:02 2019
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity KnightRider is
port (
Clk : in std_logic;
En : in std_logic;
LED : out std_logic_vector(3 downto 0));
end entity KnightRider;
--------------------------------------------------------------------------------
-- Object : Architecture design.KnightRider.structure
-- Last modified : Thu Nov 14 16:30:02 2019
--------------------------------------------------------------------------------
architecture structure of KnightRider is
begin
Process (Clk)
Variable Cnt : Unsigned(3 Downto 0) := (Others => '0');
Begin
If Rising_Edge(Clk) Then
If En = '1' Then
If (Cnt = x"6") Then
Cnt := (Others => '0');
Else
Cnt := Cnt + 1;
End If;
End If;
Case Cnt is
when X"0" => LED <= "0001";
when X"1" => LED <= "0010";
when x"2" => LED <= "0100";
when x"3" => LED <= "1000";
when x"4" => LED <= "0100";
when x"5" => LED <= "0010";
when others => LED <= "0001";
End Case ;
End If;
End Process;
end architecture structure ; -- of KnightRider
--------------------------------------------------------------------------------
-- Object : Entity design.AndInv
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AndInv is
port (
A : in std_logic;
Bn : in std_logic;
O : out std_logic);
end entity AndInv;
--------------------------------------------------------------------------------
-- Object : Architecture design.AndInv.rtl
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------
architecture rtl of AndInv is
begin
O <= A And NOT Bn;
end architecture rtl ; -- of AndInv
--------------------------------------------------------------------------------
-- Object : Entity design.Reg1
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Reg1 is
port (
Clk : in std_logic;
D : in std_logic;
Q : out std_logic);
end entity Reg1;
--------------------------------------------------------------------------------
-- Object : Architecture design.Reg1.structure
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------
architecture structure of Reg1 is
begin
Process (Clk)
Begin
If Rising_Edge(Clk) Then
Q <= D;
End If;
End Process;
end architecture structure ; -- of Reg1
--------------------------------------------------------------------------------
-- Object : Entity design.Counter
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Counter is
port (
Clk : in std_logic;
Q : out std_logic_vector(31 downto 0));
end entity Counter;
--------------------------------------------------------------------------------
-- Object : Architecture design.Counter.rtl
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------
architecture rtl of Counter is
begin
Process (Clk)
Variable Count: Unsigned(31 downto 0) := (Others => '0');
Begin
If Rising_Edge(Clk) Then
Count := Count + 1;
End If;
Q <= Std_Logic_Vector (Count);
End Process;
end architecture rtl ; -- of Counter
--------------------------------------------------------------------------------
-- Object : Entity design.spec7_blink
-- Last modified : Tue Nov 26 16:59:44 2019
--------------------------------------------------------------------------------
library ieee, unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.VCOMPONENTS.all;
entity spec7_blink is
generic(
Q : natural := 24);
port (
CLK_DMTD_N : in std_logic;
CLK_DMTD_P : in std_logic;
LED : out std_logic_vector(3 downto 0);
prsnt_m2c_l_i : in std_logic;
suicide_n_o : out std_logic;
wdog_n_o : out std_logic);
end entity spec7_blink;
--------------------------------------------------------------------------------
-- Object : Architecture design.spec7_blink.structure
-- Last modified : Tue Nov 26 16:59:44 2019
--------------------------------------------------------------------------------
architecture structure of spec7_blink is
signal O : std_ulogic;
signal u0_Q : std_logic_vector(31 downto 0);
signal u2_Q : std_logic;
signal u3_O : std_logic;
component Counter
port (
Clk : in std_logic;
Q : out std_logic_vector(31 downto 0));
end component Counter;
component Reg1
port (
Clk : in std_logic;
D : in std_logic;
Q : out std_logic);
end component Reg1;
component AndInv
port (
A : in std_logic;
Bn : in std_logic;
O : out std_logic);
end component AndInv;
component KnightRider
port (
Clk : in std_logic;
En : in std_logic;
LED : out std_logic_vector(3 downto 0));
end component KnightRider;
begin
--For normal operation choose Q24 (@ 200 MHz)
--For quick simulation choose Q4
--PRSNT_M2C_L must be defined as input.
--Driving this pin closes the TDO line to the JTAG programmer if there is no FMC card on board
--
suicide_n_o <= '1';
wdog_n_o <= '1';
u0: Counter
port map(
Clk => O,
Q => u0_Q);
u2: Reg1
port map(
Clk => O,
D => u0_Q(Q),
Q => u2_Q);
u3: AndInv
port map(
A => u0_Q(Q),
Bn => u2_Q,
O => u3_O);
u1: KnightRider
port map(
Clk => O,
En => u3_O,
LED => LED);
u4: IBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
DIFF_TERM => TRUE,
IBUF_DELAY_VALUE => "0",
IBUF_LOW_PWR => TRUE,
IFD_DELAY_VALUE => "AUTO",
IOSTANDARD => "DEFAULT",
DQS_BIAS => "FALSE")
port map(
O => O,
I => CLK_DMTD_P,
IB => CLK_DMTD_N);
end architecture structure ; -- of spec7_blink
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/spec7.lib
/*.bram
/*.mem
/*.bak
/*.wlf
/*.vstf
/*.lnk
/transcript
\ No newline at end of file
hdl/spec7_test/sim/VSim_Functional.tcl → hdl/spec7_ref_design/sim/VSim_Functional.tcl
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......@@ -18,7 +18,8 @@ puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\e
# Generate a "lm32_memory.mem" file from the "elf" file content
# Note that ISE 12.4 data2mem produces wrong results; use an older version:
#exec cmd.exe /c ..\\Software\\data2mem_ise10_1\\data2mem.exe -bd $elf_file_lm32_wrpc -d -o m xil_coregen_ahbrom.mem
exec cmd.exe /c data2mem.exe -bd $elf_file_lm32_wrpc -d -o m lm32_wrpc_memory.mem
#exec cmd.exe /c data2mem.exe -bd $elf_file_lm32_wrpc -d -o m lm32_wrpc_memory.mem
#exec cmd.exe /c updatemem -data $elf_file_lm32_wrpc -meminfo top1.smi -proc $lm32_wrpc_instpath -out lm32_wrpc_memory.mem -force
# Convert the "mem" to a "bram" (a format used by the White Rabbit "memory_loader_pkg.vhd")
do mem2bram.tcl lm32_wrpc_memory
......@@ -28,7 +29,10 @@ do mem2bram.tcl lm32_wrpc_memory
# Note that "-L unisim" is needed to find the primitive "BSCANE2" thta is instantiated in "$LM32_Sources/platform/kintex7/jtag_tap.v "
#suppress warning Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value <> is not in bounds of NATURAL.
#suppress warning Warning: (vsim-8684) No drivers exist on out port <blabla>
vsim -voptargs="+acc" -novopt \
# -novopt is now deprecated
#vsim -voptargs="+acc" -novopt
vsim -voptargs="+acc=lnprv" \
-G/spec7_wr_ref_top/g_simulation=$g_simulation \
-G/spec7_wr_ref_top/g_dpram_initf=lm32_wrpc_memory.bram \
-t ps -L unisim -lib work work.spec7_wr_ref_top
......@@ -39,7 +43,7 @@ do test.tcl
view signals
run 100 us
#run 100 us
#stop
......
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/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
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Synthesis and Place&Route README.TXT January 25, 2018
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_elf.cmd combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
4) do_vivado_prog.cmd download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
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rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
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rem prog.cmd PeterJ, 29-Dec-2019.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_mmi_elf.log
set proj_name="spec7_wr_ref_top"
set lm32_wrpc_elf="../../../sw/embedded/precompiled/wrps-sw_spec7/wrc.elf"
set lm32_wrpc_instpath="lm32_wrpc_memory"
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
%VIVADO%updatemem -meminfo %proj_name%.mmi -data %lm32_wrpc_elf% -bit %proj_name%.bit -proc %lm32_wrpc_instpath% -out %proj_name%_elf.bit -force >> vivado_mmi_elf.log
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rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
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rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
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......@@ -7,7 +7,7 @@
set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set lm32_wrpc_initf [pwd]/../../../sw/embedded/precompiled/wrps-sw_v4_2_KPx5/wrc.bram
set lm32_wrpc_initf [pwd]/../../../sw/embedded/precompiled/wrps-sw_spec7/wrc.bram
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
......@@ -18,3 +18,4 @@ if {$argc == 0 || $argv != "no_update_revision"} {
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
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/spec7_write.lib
/*.bram
/*.mem
/*.bak
/*.wlf
/*.vstf
/*.lnk
/transcript
\ No newline at end of file
hdl/spec7_write_design/sim/VSim_Functional.tcl
View file @ f56230d9
......@@ -18,7 +18,8 @@ puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\e
# Generate a "lm32_memory.mem" file from the "elf" file content
# Note that ISE 12.4 data2mem produces wrong results; use an older version:
#exec cmd.exe /c ..\\Software\\data2mem_ise10_1\\data2mem.exe -bd $elf_file_lm32_wrpc -d -o m xil_coregen_ahbrom.mem
exec cmd.exe /c data2mem.exe -bd $elf_file_lm32_wrpc -d -o m lm32_wrpc_memory.mem
#exec cmd.exe /c data2mem.exe -bd $elf_file_lm32_wrpc -d -o m lm32_wrpc_memory.mem
#exec cmd.exe /c updatemem -data $elf_file_lm32_wrpc -meminfo top1.smi -proc $lm32_wrpc_instpath -out lm32_wrpc_memory.mem -force
# Convert the "mem" to a "bram" (a format used by the White Rabbit "memory_loader_pkg.vhd")
do mem2bram.tcl lm32_wrpc_memory
......@@ -28,7 +29,15 @@ do mem2bram.tcl lm32_wrpc_memory
# Note that "-L unisim" is needed to find the primitive "BSCANE2" thta is instantiated in "$LM32_Sources/platform/kintex7/jtag_tap.v "
#suppress warning Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value <> is not in bounds of NATURAL.
#suppress warning Warning: (vsim-8684) No drivers exist on out port <blabla>
vsim -voptargs="+acc" -novopt \
#vsim -G/spec7_write_top/g_simulation=$g_simulation -G/spec7_write_top/g_dpram_initf=lm32_wrpc_memory.bram -t ps -L unisim -lib work work.spec7_write_top
# -novopt is now deprecated
#vsim -voptargs="+acc" -novopt
# Note that -novopt can cause errors like:
# "Error: (vsim-8346) .../blabla.vhd(516): VHDL component port was not found because Verilog port 'D_ACK_I' was mapped to the extended identifier '\D_ACK_I\'."
# "Error: (vsim-3935) .../blabla.vhd(177): Port 'I_CYC_O' not found in the connected module."
vsim -voptargs="+acc=lnprv" \
-G/spec7_write_top/g_simulation=$g_simulation \
-G/spec7_write_top/g_dpram_initf=lm32_wrpc_memory.bram \
-t ps -L unisim -lib work work.spec7_write_top
......
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+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi
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sw/scripts/viv_do_all.tcl
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