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SPEC7
Commit e2992685 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Add SPEC7 PCIe Tandem Boot auxiliary design

parent c2053a22
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hdl/ip/processing_system_pcie_tandem_boot.bd 0 → 100644
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{
"design": {
"design_info": {
"boundary_crc": "0xE176D980E11BED4F",
"device": "xc7z035fbg676-1",
"name": "processing_system_pcie_tandem_boot",
"synth_flow_mode": "Hierarchical",
"tool_version": "2019.2",
"validated": "true"
},
"design_tree": {
"pcie_7x": "",
"ps7": "",
"util_ds_buf_0": "",
"xlconstant_0": ""
},
"interface_ports": {
"DDR": {
"mode": "Master",
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"TIMEPERIOD_PS": {
"value": "1250",
"value_src": "default"
},
"MEMORY_TYPE": {
"value": "COMPONENTS",
"value_src": "default"
},
"DATA_WIDTH": {
"value": "8",
"value_src": "default"
},
"CS_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_MASK_ENABLED": {
"value": "true",
"value_src": "default"
},
"SLOT": {
"value": "Single",
"value_src": "default"
},
"MEM_ADDR_MAP": {
"value": "ROW_COLUMN_BANK",
"value_src": "default"
},
"BURST_LENGTH": {
"value": "8",
"value_src": "default"
},
"AXI_ARBITRATION_SCHEME": {
"value": "TDM",
"value_src": "default"
},
"CAS_LATENCY": {
"value": "11",
"value_src": "default"
},
"CAS_WRITE_LATENCY": {
"value": "11",
"value_src": "default"
}
}
},
"FIXED_IO": {
"mode": "Master",
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
}
}
}
},
"ports": {
"pci_clk_n": {
"type": "clk",
"direction": "I",
"left": "0",
"right": "0",
"parameters": {
"CLK_DOMAIN": {
"value": "processing_system_pcie_tandem_boot_pci_clk_n",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000",
"value_src": "default"
}
}
},
"pci_clk_p": {
"type": "clk",
"direction": "I",
"left": "0",
"right": "0",
"parameters": {
"CLK_DOMAIN": {
"value": "processing_system_pcie_tandem_boot_pci_clk_p",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000",
"value_src": "default"
}
}
},
"perst_n": {
"type": "rst",
"direction": "I",
"parameters": {
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "default"
}
}
},
"rxn": {
"direction": "I",
"left": "1",
"right": "0"
},
"rxp": {
"direction": "I",
"left": "1",
"right": "0"
},
"txn": {
"direction": "O",
"left": "1",
"right": "0"
},
"txp": {
"direction": "O",
"left": "1",
"right": "0"
}
},
"components": {
"pcie_7x": {
"vlnv": "xilinx.com:ip:pcie_7x:3.3",
"xci_name": "processing_system_pcie_tandem_boot_pcie_7x_0",
"parameters": {
"Bar0_64bit": {
"value": "true"
},
"Bar0_Scale": {
"value": "Megabytes"
},
"Bar0_Size": {
"value": "1"
},
"Bar2_64bit": {
"value": "true"
},
"Bar2_Enabled": {
"value": "true"
},
"Bar2_Scale": {
"value": "Kilobytes"
},
"Bar2_Size": {
"value": "64"
},
"Bar2_Type": {
"value": "Memory"
},
"Bar4_64bit": {
"value": "false"
},
"Bar4_Enabled": {
"value": "true"
},
"Bar4_Prefetchable": {
"value": "false"
},
"Bar4_Scale": {
"value": "Megabytes"
},
"Bar4_Size": {
"value": "16"
},
"Bar4_Type": {
"value": "Memory"
},
"Base_Class_Menu": {
"value": "Simple_communication_controllers"
},
"Class_Code_Base": {
"value": "07"
},
"Class_Code_Interface": {
"value": "01"
},
"Class_Code_Sub": {
"value": "00"
},
"Device_ID": {
"value": "7022"
},
"IntX_Generation": {
"value": "true"
},
"Interface_Width": {
"value": "64_bit"
},
"Legacy_Interrupt": {
"value": "INTA"
},
"Link_Speed": {
"value": "5.0_GT/s"
},
"MSI_Enabled": {
"value": "false"
},
"MSIx_PBA_BIR": {
"value": "BAR_1:0"
},
"MSIx_Table_BIR": {
"value": "BAR_1:0"
},
"Max_Payload_Size": {
"value": "512_bytes"
},
"Maximum_Link_Width": {
"value": "X2"
},
"PCIe_Blk_Locn": {
"value": "X0Y0"
},
"PCIe_Debug_Ports": {
"value": "false"
},
"Pcie_fast_config": {
"value": "Tandem_PROM (Refer PG054)"
},
"RBAR_Num": {
"value": "0"
},
"Ref_Clk_Freq": {
"value": "100_MHz"
},
"Sub_Class_Interface_Menu": {
"value": "16450_compatible_serial_controller"
},
"Trans_Buf_Pipeline": {
"value": "None"
},
"Trgt_Link_Speed": {
"value": "4'h2"
},
"User_Clk_Freq": {
"value": "125"
},
"Xlnx_Ref_Board": {
"value": "None"
},
"en_ext_clk": {
"value": "false"
},
"mode_selection": {
"value": "Advanced"
},
"rcv_msg_if": {
"value": "false"
}
}
},
"ps7": {
"vlnv": "xilinx.com:ip:processing_system7:5.5",
"xci_name": "processing_system_pcie_tandem_boot_ps7_0",
"parameters": {
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
"value": "666.666687"
},
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
"value": "10.158730"
},
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
"value": "125.000000"
},
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
"value": "50.000000"
},
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
"value": "250.000000"
},
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
"value": "177.777771"
},
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
"value": "100.000000"
},
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
"value": "100.000000"
},
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_CLK0_FREQ": {
"value": "50000000"
},
"PCW_CLK1_FREQ": {
"value": "250000000"
},
"PCW_CLK2_FREQ": {
"value": "10000000"
},
"PCW_CLK3_FREQ": {
"value": "10000000"
},
"PCW_DDR_RAM_HIGHADDR": {
"value": "0x3FFFFFFF"
},
"PCW_DUAL_PARALLEL_QSPI_DATA_MODE": {
"value": "x8"
},
"PCW_ENET0_ENET0_IO": {
"value": "MIO 16 .. 27"
},
"PCW_ENET0_GRP_MDIO_ENABLE": {
"value": "1"
},
"PCW_ENET0_GRP_MDIO_IO": {
"value": "MIO 52 .. 53"
},
"PCW_ENET0_PERIPHERAL_CLKSRC": {
"value": "IO PLL"
},
"PCW_ENET0_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_ENET0_PERIPHERAL_FREQMHZ": {
"value": "1000 Mbps"
},
"PCW_ENET0_RESET_ENABLE": {
"value": "1"
},
"PCW_ENET0_RESET_IO": {
"value": "MIO 49"
},
"PCW_ENET_RESET_ENABLE": {
"value": "1"
},
"PCW_ENET_RESET_SELECT": {
"value": "Share reset pin"
},
"PCW_EN_CLK0_PORT": {
"value": "1"
},
"PCW_EN_CLK1_PORT": {
"value": "1"
},
"PCW_EN_EMIO_CD_SDIO0": {
"value": "0"
},
"PCW_EN_EMIO_ENET0": {
"value": "0"
},
"PCW_EN_EMIO_GPIO": {
"value": "0"
},
"PCW_EN_EMIO_I2C0": {
"value": "0"
},
"PCW_EN_EMIO_TTC0": {
"value": "0"
},
"PCW_EN_EMIO_UART0": {
"value": "0"
},
"PCW_EN_EMIO_UART1": {
"value": "1"
},
"PCW_EN_EMIO_WP_SDIO0": {
"value": "0"
},
"PCW_EN_ENET0": {
"value": "1"
},
"PCW_EN_GPIO": {
"value": "1"
},
"PCW_EN_I2C0": {
"value": "1"
},
"PCW_EN_QSPI": {
"value": "1"
},
"PCW_EN_RST1_PORT": {
"value": "1"
},
"PCW_EN_SDIO0": {
"value": "1"
},
"PCW_EN_TTC0": {
"value": "0"
},
"PCW_EN_UART0": {
"value": "1"
},
"PCW_EN_UART1": {
"value": "1"
},
"PCW_EN_USB0": {
"value": "1"
},
"PCW_FCLK_CLK0_BUF": {
"value": "TRUE"
},
"PCW_FCLK_CLK1_BUF": {
"value": "TRUE"
},
"PCW_FPGA0_PERIPHERAL_FREQMHZ": {
"value": "50"
},
"PCW_FPGA1_PERIPHERAL_FREQMHZ": {
"value": "250"
},
"PCW_FPGA_FCLK0_ENABLE": {
"value": "1"
},
"PCW_FPGA_FCLK1_ENABLE": {
"value": "1"
},
"PCW_GPIO_EMIO_GPIO_ENABLE": {
"value": "0"
},
"PCW_GPIO_MIO_GPIO_ENABLE": {
"value": "1"
},
"PCW_GPIO_MIO_GPIO_IO": {
"value": "MIO"
},
"PCW_I2C0_GRP_INT_ENABLE": {
"value": "1"
},
"PCW_I2C0_GRP_INT_IO": {
"value": "EMIO"
},
"PCW_I2C0_I2C0_IO": {
"value": "MIO 14 .. 15"
},
"PCW_I2C0_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_I2C0_RESET_ENABLE": {
"value": "0"
},
"PCW_I2C_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_I2C_RESET_ENABLE": {
"value": "1"
},
"PCW_I2C_RESET_SELECT": {
"value": "Share reset pin"
},
"PCW_MIO_0_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_0_PULLUP": {
"value": "enabled"
},
"PCW_MIO_0_SLEW": {
"value": "slow"
},
"PCW_MIO_10_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_10_PULLUP": {
"value": "enabled"
},
"PCW_MIO_10_SLEW": {
"value": "slow"
},
"PCW_MIO_11_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_11_PULLUP": {
"value": "enabled"
},
"PCW_MIO_11_SLEW": {
"value": "slow"
},
"PCW_MIO_12_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_12_PULLUP": {
"value": "enabled"
},
"PCW_MIO_12_SLEW": {
"value": "slow"
},
"PCW_MIO_13_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_13_PULLUP": {
"value": "enabled"
},
"PCW_MIO_13_SLEW": {
"value": "slow"
},
"PCW_MIO_14_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_14_PULLUP": {
"value": "enabled"
},
"PCW_MIO_14_SLEW": {
"value": "slow"
},
"PCW_MIO_15_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_15_PULLUP": {
"value": "enabled"
},
"PCW_MIO_15_SLEW": {
"value": "slow"
},
"PCW_MIO_16_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_16_PULLUP": {
"value": "enabled"
},
"PCW_MIO_16_SLEW": {
"value": "slow"
},
"PCW_MIO_17_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_17_PULLUP": {
"value": "enabled"
},
"PCW_MIO_17_SLEW": {
"value": "slow"
},
"PCW_MIO_18_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_18_PULLUP": {
"value": "enabled"
},
"PCW_MIO_18_SLEW": {
"value": "slow"
},
"PCW_MIO_19_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_19_PULLUP": {
"value": "enabled"
},
"PCW_MIO_19_SLEW": {
"value": "slow"
},
"PCW_MIO_1_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_1_PULLUP": {
"value": "enabled"
},
"PCW_MIO_1_SLEW": {
"value": "slow"
},
"PCW_MIO_20_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_20_PULLUP": {
"value": "enabled"
},
"PCW_MIO_20_SLEW": {
"value": "slow"
},
"PCW_MIO_21_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_21_PULLUP": {
"value": "enabled"
},
"PCW_MIO_21_SLEW": {
"value": "slow"
},
"PCW_MIO_22_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_22_PULLUP": {
"value": "enabled"
},
"PCW_MIO_22_SLEW": {
"value": "slow"
},
"PCW_MIO_23_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_23_PULLUP": {
"value": "enabled"
},
"PCW_MIO_23_SLEW": {
"value": "slow"
},
"PCW_MIO_24_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_24_PULLUP": {
"value": "enabled"
},
"PCW_MIO_24_SLEW": {
"value": "slow"
},
"PCW_MIO_25_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_25_PULLUP": {
"value": "enabled"
},
"PCW_MIO_25_SLEW": {
"value": "slow"
},
"PCW_MIO_26_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_26_PULLUP": {
"value": "enabled"
},
"PCW_MIO_26_SLEW": {
"value": "slow"
},
"PCW_MIO_27_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_27_PULLUP": {
"value": "enabled"
},
"PCW_MIO_27_SLEW": {
"value": "slow"
},
"PCW_MIO_28_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_28_PULLUP": {
"value": "enabled"
},
"PCW_MIO_28_SLEW": {
"value": "slow"
},
"PCW_MIO_29_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_29_PULLUP": {
"value": "enabled"
},
"PCW_MIO_29_SLEW": {
"value": "slow"
},
"PCW_MIO_2_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_2_SLEW": {
"value": "slow"
},
"PCW_MIO_30_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_30_PULLUP": {
"value": "enabled"
},
"PCW_MIO_30_SLEW": {
"value": "slow"
},
"PCW_MIO_31_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_31_PULLUP": {
"value": "enabled"
},
"PCW_MIO_31_SLEW": {
"value": "slow"
},
"PCW_MIO_32_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_32_PULLUP": {
"value": "enabled"
},
"PCW_MIO_32_SLEW": {
"value": "slow"
},
"PCW_MIO_33_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_33_PULLUP": {
"value": "enabled"
},
"PCW_MIO_33_SLEW": {
"value": "slow"
},
"PCW_MIO_34_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_34_PULLUP": {
"value": "enabled"
},
"PCW_MIO_34_SLEW": {
"value": "slow"
},
"PCW_MIO_35_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_35_PULLUP": {
"value": "enabled"
},
"PCW_MIO_35_SLEW": {
"value": "slow"
},
"PCW_MIO_36_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_36_PULLUP": {
"value": "enabled"
},
"PCW_MIO_36_SLEW": {
"value": "slow"
},
"PCW_MIO_37_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_37_PULLUP": {
"value": "enabled"
},
"PCW_MIO_37_SLEW": {
"value": "slow"
},
"PCW_MIO_38_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_38_PULLUP": {
"value": "enabled"
},
"PCW_MIO_38_SLEW": {
"value": "slow"
},
"PCW_MIO_39_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_39_PULLUP": {
"value": "enabled"
},
"PCW_MIO_39_SLEW": {
"value": "slow"
},
"PCW_MIO_3_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_3_SLEW": {
"value": "slow"
},
"PCW_MIO_40_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_40_PULLUP": {
"value": "enabled"
},
"PCW_MIO_40_SLEW": {
"value": "slow"
},
"PCW_MIO_41_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_41_PULLUP": {
"value": "enabled"
},
"PCW_MIO_41_SLEW": {
"value": "slow"
},
"PCW_MIO_42_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_42_PULLUP": {
"value": "enabled"
},
"PCW_MIO_42_SLEW": {
"value": "slow"
},
"PCW_MIO_43_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_43_PULLUP": {
"value": "enabled"
},
"PCW_MIO_43_SLEW": {
"value": "slow"
},
"PCW_MIO_44_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_44_PULLUP": {
"value": "enabled"
},
"PCW_MIO_44_SLEW": {
"value": "slow"
},
"PCW_MIO_45_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_45_PULLUP": {
"value": "enabled"
},
"PCW_MIO_45_SLEW": {
"value": "slow"
},
"PCW_MIO_46_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_46_PULLUP": {
"value": "enabled"
},
"PCW_MIO_46_SLEW": {
"value": "slow"
},
"PCW_MIO_47_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_47_PULLUP": {
"value": "enabled"
},
"PCW_MIO_47_SLEW": {
"value": "slow"
},
"PCW_MIO_48_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_48_PULLUP": {
"value": "enabled"
},
"PCW_MIO_48_SLEW": {
"value": "slow"
},
"PCW_MIO_49_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_49_PULLUP": {
"value": "enabled"
},
"PCW_MIO_49_SLEW": {
"value": "slow"
},
"PCW_MIO_4_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_4_SLEW": {
"value": "slow"
},
"PCW_MIO_50_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_50_PULLUP": {
"value": "enabled"
},
"PCW_MIO_50_SLEW": {
"value": "slow"
},
"PCW_MIO_51_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_51_PULLUP": {
"value": "enabled"
},
"PCW_MIO_51_SLEW": {
"value": "slow"
},
"PCW_MIO_52_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_52_PULLUP": {
"value": "enabled"
},
"PCW_MIO_52_SLEW": {
"value": "slow"
},
"PCW_MIO_53_IOTYPE": {
"value": "LVCMOS 2.5V"
},
"PCW_MIO_53_PULLUP": {
"value": "enabled"
},
"PCW_MIO_53_SLEW": {
"value": "slow"
},
"PCW_MIO_5_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_5_SLEW": {
"value": "slow"
},
"PCW_MIO_6_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_6_SLEW": {
"value": "slow"
},
"PCW_MIO_7_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_7_SLEW": {
"value": "slow"
},
"PCW_MIO_8_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_8_SLEW": {
"value": "slow"
},
"PCW_MIO_9_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_9_PULLUP": {
"value": "enabled"
},
"PCW_MIO_9_SLEW": {
"value": "slow"
},
"PCW_MIO_TREE_PERIPHERALS": {
"value": "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#ENET Reset#UART 0#UART 0#Enet 0#Enet 0"
},
"PCW_MIO_TREE_SIGNALS": {
"value": "qspi1_ss_b#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#qspi1_sclk#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#wp#cd#reset#reset#rx#tx#mdc#mdio"
},
"PCW_PRESET_BANK1_VOLTAGE": {
"value": "LVCMOS 2.5V"
},
"PCW_QSPI_GRP_FBCLK_ENABLE": {
"value": "1"
},
"PCW_QSPI_GRP_FBCLK_IO": {
"value": "MIO 8"
},
"PCW_QSPI_GRP_IO1_ENABLE": {
"value": "1"
},
"PCW_QSPI_GRP_IO1_IO": {
"value": "MIO 0 9 .. 13"
},
"PCW_QSPI_GRP_SINGLE_SS_ENABLE": {
"value": "0"
},
"PCW_QSPI_GRP_SS1_ENABLE": {
"value": "0"
},
"PCW_QSPI_INTERNAL_HIGHADDRESS": {
"value": "0xFDFFFFFF"
},
"PCW_QSPI_PERIPHERAL_CLKSRC": {
"value": "DDR PLL"
},
"PCW_QSPI_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_QSPI_PERIPHERAL_FREQMHZ": {
"value": "180"
},
"PCW_QSPI_QSPI_IO": {
"value": "MIO 1 .. 6"
},
"PCW_SD0_GRP_CD_ENABLE": {
"value": "1"
},
"PCW_SD0_GRP_CD_IO": {
"value": "MIO 47"
},
"PCW_SD0_GRP_POW_ENABLE": {
"value": "0"
},
"PCW_SD0_GRP_WP_ENABLE": {
"value": "1"
},
"PCW_SD0_GRP_WP_IO": {
"value": "MIO 46"
},
"PCW_SD0_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_SD0_SD0_IO": {
"value": "MIO 40 .. 45"
},
"PCW_SDIO_PERIPHERAL_FREQMHZ": {
"value": "100"
},
"PCW_SDIO_PERIPHERAL_VALID": {
"value": "1"
},
"PCW_S_AXI_HP0_DATA_WIDTH": {
"value": "64"
},
"PCW_TTC0_PERIPHERAL_ENABLE": {
"value": "0"
},
"PCW_UART0_GRP_FULL_ENABLE": {
"value": "0"
},
"PCW_UART0_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_UART0_UART0_IO": {
"value": "MIO 50 .. 51"
},
"PCW_UART1_GRP_FULL_ENABLE": {
"value": "0"
},
"PCW_UART1_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_UART1_UART1_IO": {
"value": "EMIO"
},
"PCW_UART_PERIPHERAL_FREQMHZ": {
"value": "100"
},
"PCW_UART_PERIPHERAL_VALID": {
"value": "1"
},
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
"value": "533.333374"
},
"PCW_UIPARAM_DDR_PARTNO": {
"value": "MT41K256M16 RE-125"
},
"PCW_USB0_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_USB0_RESET_ENABLE": {
"value": "1"
},
"PCW_USB0_RESET_IO": {
"value": "MIO 48"
},
"PCW_USB0_USB0_IO": {
"value": "MIO 28 .. 39"
},
"PCW_USB_RESET_ENABLE": {
"value": "1"
},
"PCW_USB_RESET_SELECT": {
"value": "Share reset pin"
},
"PCW_USE_DEFAULT_ACP_USER_VAL": {
"value": "1"
},
"PCW_USE_M_AXI_GP0": {
"value": "1"
},
"PCW_USE_M_AXI_GP1": {
"value": "1"
},
"PCW_USE_S_AXI_ACP": {
"value": "1"
},
"PCW_USE_S_AXI_GP0": {
"value": "1"
},
"PCW_USE_S_AXI_HP0": {
"value": "1"
},
"preset": {
"value": "None"
}
}
},
"util_ds_buf_0": {
"vlnv": "xilinx.com:ip:util_ds_buf:2.1",
"xci_name": "processing_system_pcie_tandem_boot_util_ds_buf_0_0",
"parameters": {
"C_BUF_TYPE": {
"value": "IBUFDSGTE"
}
}
},
"xlconstant_0": {
"vlnv": "xilinx.com:ip:xlconstant:1.1",
"xci_name": "processing_system_pcie_tandem_boot_xlconstant_0_0",
"parameters": {
"CONST_VAL": {
"value": "0"
}
}
}
},
"interface_nets": {
"processing_system7_0_FIXED_IO": {
"interface_ports": [
"FIXED_IO",
"ps7/FIXED_IO"
]
},
"processing_system7_0_DDR": {
"interface_ports": [
"DDR",
"ps7/DDR"
]
}
},
"nets": {
"IBUF_DS_N_0_1": {
"ports": [
"pci_clk_n",
"util_ds_buf_0/IBUF_DS_N"
]
},
"IBUF_DS_P_0_1": {
"ports": [
"pci_clk_p",
"util_ds_buf_0/IBUF_DS_P"
]
},
"pci_exp_rxn_0_1": {
"ports": [
"rxn",
"pcie_7x/pci_exp_rxn"
]
},
"pci_exp_rxp_0_1": {
"ports": [
"rxp",
"pcie_7x/pci_exp_rxp"
]
},
"pcie_7x_pci_exp_txn": {
"ports": [
"pcie_7x/pci_exp_txn",
"txn"
]
},
"pcie_7x_pci_exp_txp": {
"ports": [
"pcie_7x/pci_exp_txp",
"txp"
]
},
"processing_system7_0_FCLK_CLK0": {
"ports": [
"ps7/FCLK_CLK0",
"ps7/M_AXI_GP0_ACLK",
"ps7/S_AXI_GP0_ACLK",
"ps7/S_AXI_HP0_ACLK",
"ps7/S_AXI_ACP_ACLK"
]
},
"sys_rst_n_1": {
"ports": [
"perst_n",
"pcie_7x/sys_rst_n"
]
},
"util_ds_buf_0_IBUF_OUT": {
"ports": [
"util_ds_buf_0/IBUF_OUT",
"pcie_7x/sys_clk"
]
},
"ps7_FCLK_CLK1": {
"ports": [
"ps7/FCLK_CLK1",
"ps7/M_AXI_GP1_ACLK"
]
},
"xlconstant_0_dout": {
"ports": [
"xlconstant_0/dout",
"pcie_7x/s_axis_tx_tvalid"
]
}
},
"addressing": {
"/ps7": {
"address_spaces": {
"Data": {
"range": "4G",
"width": "32"
}
}
}
}
}
}
hdl/syn/spec7_tandem_boot/.gitignore 0 → 100644
View file @ e2992685
/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/revisiondate_log.txt
/hdl_version.xdc
hdl/syn/spec7_tandem_boot/Manifest.py 0 → 100644
View file @ e2992685
board = "spec7"
target = "xilinx"
action = "synthesis"
syn_device = "xc7z035"
syn_grade = "-1"
syn_package = "fbg676"
syn_top = "spec7_tandem_boot_top"
syn_project = "spec7_tandem_boot_top.xpr"
syn_tool = "vivado"
modules = { "local" : "../../top/spec7_tandem_boot/"}
hdl/syn/spec7_tandem_boot/README.TXT 0 → 100644
View file @ e2992685
Synthesis and Place&Route README.TXT January 25, 2018
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_elf.cmd combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
4) do_vivado_prog.cmd download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
hdl/syn/spec7_tandem_boot/do_vivado.cmd 0 → 100644
View file @ e2992685
rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
hdl/syn/spec7_tandem_boot/do_vivado_gen_bin_mcs.cmd 0 → 100644
View file @ e2992685
rem prog.cmd PeterJ, 23-JUl-2018.
@prompt $$$s
rem ### Clean up old log files and stuff
del vivado_gen_bin_mcs.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_gen_bin_mcs.tcl -log vivado_gen_bin_mcs.log
hdl/syn/spec7_tandem_boot/do_vivado_prog.cmd 0 → 100644
View file @ e2992685
rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
hdl/syn/spec7_tandem_boot/do_vivado_tcl.cmd 0 → 100644
View file @ e2992685
rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
hdl/syn/spec7_tandem_boot/proj_file_list.txt 0 → 100644
View file @ e2992685
# From directory ....spec7/hdl/syn/spec7_tandem_boot
# hdlmake list-files > proj_file_list.txt
../../top/spec7_tandem_boot/spec7_tandem_boot_top.vhd
../../top/spec7_tandem_boot/spec7_tandem_boot_top.xdc
# bmm not supported by hdlmake? Need to add it manually...
../../ip/processing_system_pcie_tandem_boot.bd
# include hardware version ID un FPGA USER_ID register:
hdl_version.xdc
hdl/syn/spec7_tandem_boot/proj_properties.tcl 0 → 100644
View file @ e2992685
#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================
# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
set spec7_design spec7_tandem_boot_top
# ====================================================
# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================
set proj_name spec7_tandem_boot_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_design=$spec7_design"
}
hdl/top/spec7_tandem_boot/Manifest.py 0 → 100644
View file @ e2992685
files = [
"spec7_tandem_boot_top.vhd",
"spec7_tandem_boot_top.xdc",
]
hdl/top/spec7_tandem_boot/spec7_tandem_boot_top.vhd 0 → 100644
View file @ e2992685
-------------------------------------------------------------------------------
-- Title : Tandem Boot for SPEC7
-- : based on ZYNQ Z030/Z035/Z045
-- Project : WR PTP Core and EMPIR 17IND14 WRITE
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-- : http://empir.npl.co.uk/write/
-------------------------------------------------------------------------------
-- File : spec7_tandem_boot_top.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- : Mamta Ramendra Shukla <mamta.ramendra.shukla@cern.ch>
-- : Javier D. Garcia <jgarcia@gl-research.com>
-- Company : Nikhef, CERN
-- Created : 2021-06-27
-- Last update: 2021-06-27
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for Tandem Boot for SPEC7.
-- See also EMPIR 17IND14 WRITE Project (http://empir.npl.co.uk/write/)
--
-- This Tandem Boot design is a bare minimal PCIe core that enables early
-- PCIe enumeration for the SPEC7 by providing a Tandem PROM mode boot design
-- that reserves the appropriated BAR sizes for SPEC7 designs based on the
-- non Tandem capable Xilinx XDMA core that are loaded afterwards.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2021 Nikhef, CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_tandem_boot_top is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
pci_clk_n : in STD_LOGIC_VECTOR ( 0 to 0 );
pci_clk_p : in STD_LOGIC_VECTOR ( 0 to 0 );
perst_n : in STD_LOGIC;
rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end spec7_tandem_boot_top;
architecture STRUCTURE of spec7_tandem_boot_top is
component processing_system_pcie_tandem_boot_wrapper is
port (
pci_clk_n : in STD_LOGIC_VECTOR ( 0 to 0 );
pci_clk_p : in STD_LOGIC_VECTOR ( 0 to 0 );
perst_n : in STD_LOGIC;
rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component processing_system_pcie_tandem_boot_wrapper;
begin
processing_system_pcie_tandem_boot_wrapper_i: component processing_system_pcie_tandem_boot_wrapper
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
pci_clk_n(0) => pci_clk_n(0),
pci_clk_p(0) => pci_clk_p(0),
perst_n => perst_n,
rxn(1 downto 0) => rxn(1 downto 0),
rxp(1 downto 0) => rxp(1 downto 0),
txn(1 downto 0) => txn(1 downto 0),
txp(1 downto 0) => txp(1 downto 0)
);
end STRUCTURE;
hdl/top/spec7_tandem_boot/spec7_tandem_boot_top.xdc 0 → 100644
View file @ e2992685
# ---------------------------------------------------------------------------`
# -- Clocks/resets
# ---------------------------------------------------------------------------
# Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
#set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
# ---------------------------------------------------------------------------
# -- PCIe
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
set_property PACKAGE_PIN AB3 [get_ports {rxn[0]}]
set_property PACKAGE_PIN AB4 [get_ports {rxp[0]}]
set_property PACKAGE_PIN AA1 [get_ports {txn[0]}]
set_property PACKAGE_PIN AA2 [get_ports {txp[0]}]
set_property PACKAGE_PIN Y3 [get_ports {rxn[1]}]
set_property PACKAGE_PIN Y4 [get_ports {rxp[1]}]
set_property PACKAGE_PIN W1 [get_ports {txn[1]}]
set_property PACKAGE_PIN W2 [get_ports {txp[1]}]
set_property PACKAGE_PIN R6 [get_ports pci_clk_p]
set_property PACKAGE_PIN R5 [get_ports pci_clk_n]
create_clock -period 10.000 -name pci_clk_p [get_ports pci_clk_p]
set_property PACKAGE_PIN D13 [get_ports perst_n]
set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
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