Add SPEC7 PCIe Tandem Boot auxiliary design

e2992685 · Javier D. Garcia-Lasheras · c2053a22 · e2992685 · e2992685 · e2992685
Commit e2992685 authored Jun 27, 2021 by Javier D. Garcia-Lasheras
13 changed files
--- a/hdl/ip/processing_system_pcie_tandem_boot.bd
+++ b/hdl/ip/processing_system_pcie_tandem_boot.bd
--- a/hdl/syn/spec7_tandem_boot/.gitignore
+++ b/hdl/syn/spec7_tandem_boot/.gitignore
+/.Xil
+/work
+/*.bak
+/*.jou
+/*.log
+/*.prm
+/*.mcs
+/*.bin
+/*.bit
+/revisiondate_log.txt
+/hdl_version.xdc
--- a/hdl/syn/spec7_tandem_boot/Manifest.py
+++ b/hdl/syn/spec7_tandem_boot/Manifest.py
+board  = "spec7"
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc7z035"
+syn_grade = "-1"
+syn_package = "fbg676"
+
+syn_top = "spec7_tandem_boot_top"
+syn_project = "spec7_tandem_boot_top.xpr"
+
+syn_tool = "vivado"
+
+modules = { "local" : "../../top/spec7_tandem_boot/"}
--- a/hdl/syn/spec7_tandem_boot/README.TXT
+++ b/hdl/syn/spec7_tandem_boot/README.TXT
+Synthesis and Place&Route README.TXT 		January 25, 2018
+--------------------------------------------------------
+
+Scripts:
+--------
+1) do_vivado.cmd          start vivado (calling viv_do_all.tcl)
+2) do_vivado_tcl.cmd      start vivado tcl console.
+                          You may want to type:
+                          a) "start_gui" to start the vivado gui
+                          b) "source proj_properties.tcl" to find the path to the scripts and next
+                             "source $script_dir/viv_do_all.tcl"
+3) do_elf.cmd             combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
+                          and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
+4) do_vivado_prog.cmd     download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
+                          download cable.
+Project info and sources:
+--------
+proj_properties.tcl       contains the project properties (name, device etc.)
+proj_file_list.txt        a text file with all project sources. Remember that the wr-cores files are listed
+                          using "hdlmake list-files > proj_file_list.txt" in
+                          directory "../../wr-cores/syn/clbv3_ref_design"
+                          
+Scripts that are called by the scripts above or can be executed separately on the tcl command line:                          
+--------
+viv_do_synt.tcl           sourced by viv_do_all.tcl, starts vivado synthesis run
+viv_do_impl.tcl           sourced by viv_do_all.tcl, starts vivado implementation run
+viv_do_program.tcl        sourced by do_vivado_prog.cmd
--- a/hdl/syn/spec7_tandem_boot/do_vivado.cmd
+++ b/hdl/syn/spec7_tandem_boot/do_vivado.cmd
+rem do_vivado.cmd  PeterJ,    19-Jan-2018.
+@prompt $$$s
+
+rem ### Cleanup old log files and stuff
+del *.log
+del *.jou
+
+rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
+rem ### in your (User) Environment Variables
+"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
--- a/hdl/syn/spec7_tandem_boot/do_vivado_gen_bin_mcs.cmd
+++ b/hdl/syn/spec7_tandem_boot/do_vivado_gen_bin_mcs.cmd
+rem prog.cmd  PeterJ,    23-JUl-2018.
+@prompt $$$s
+
+rem ### Clean up old log files and stuff
+del vivado_gen_bin_mcs.log
+
+rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
+rem ### in your (User) Environment Variables
+"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_gen_bin_mcs.tcl -log vivado_gen_bin_mcs.log
--- a/hdl/syn/spec7_tandem_boot/do_vivado_prog.cmd
+++ b/hdl/syn/spec7_tandem_boot/do_vivado_prog.cmd
+rem prog.cmd  PeterJ,    23-Jan-2018.
+@prompt $$$s
+
+rem ### Cleanup old log files and stuff
+del vivado_prog.log
+
+rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
+rem ### in your (User) Environment Variables
+"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
--- a/hdl/syn/spec7_tandem_boot/do_vivado_tcl.cmd
+++ b/hdl/syn/spec7_tandem_boot/do_vivado_tcl.cmd
+rem do_vivado_tcl.cmd  PeterJ,    19-Jan-2018.
+@prompt $$$s
+
+rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
+rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
+rem set DesName=clbv3_wr_ref_top
+
+rem set LogName=%DesName%-vivado
+
+rem ### Cleanup old log files and stuff (
+rem del vivado*.log
+rem del vivado*.jou
+
+rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
+rem ### in your (User) Environment Variables
+"%VIVADO%\vivado.bat" -mode tcl
--- a/hdl/syn/spec7_tandem_boot/proj_file_list.txt
+++ b/hdl/syn/spec7_tandem_boot/proj_file_list.txt
+# From directory ....spec7/hdl/syn/spec7_tandem_boot
+# hdlmake list-files > proj_file_list.txt
+
+../../top/spec7_tandem_boot/spec7_tandem_boot_top.vhd
+../../top/spec7_tandem_boot/spec7_tandem_boot_top.xdc
+
+# bmm not supported by hdlmake? Need to add it manually...
+../../ip/processing_system_pcie_tandem_boot.bd
+
+# include hardware version ID un FPGA USER_ID register:
+hdl_version.xdc
--- a/hdl/syn/spec7_tandem_boot/proj_properties.tcl
+++ b/hdl/syn/spec7_tandem_boot/proj_properties.tcl
+#
+# projetc_properties.tcl
+# This file contains the general project properties such as the project name and
+# the directory where Vivado is doing it's job
+#
+# ====================================================
+
+# ====================================================
+# SELECT DESIGN TO BUILD:
+# ====================================================
+set spec7_design spec7_tandem_boot_top
+# ====================================================
+
+# ====================================================
+# SELECT DEVICE TO BUILD:
+# ====================================================
+# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
+set device xc7z035fbg676-1
+#set device xc7z030fbg676-1
+# ====================================================
+
+set proj_name spec7_tandem_boot_top
+set proj_dir work
+set script_dir [pwd]/../../../sw/scripts
+
+# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
+if {$argc == 0 || $argv != "no_update_revision"} {
+  source $script_dir/revisiondate.tcl
+
+  set generics "g_design=$spec7_design"
+}
--- a/hdl/top/spec7_tandem_boot/Manifest.py
+++ b/hdl/top/spec7_tandem_boot/Manifest.py
+files = [
+    "spec7_tandem_boot_top.vhd",
+    "spec7_tandem_boot_top.xdc",
+]
--- a/hdl/top/spec7_tandem_boot/spec7_tandem_boot_top.vhd
+++ b/hdl/top/spec7_tandem_boot/spec7_tandem_boot_top.vhd
+-------------------------------------------------------------------------------
+-- Title      : Tandem Boot for SPEC7
+--            : based on ZYNQ Z030/Z035/Z045
+-- Project    : WR PTP Core and EMPIR 17IND14 WRITE 
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+--            : http://empir.npl.co.uk/write/
+-------------------------------------------------------------------------------
+-- File       : spec7_tandem_boot_top.vhd
+-- Author(s)  : Peter Jansweijer <peterj@nikhef.nl>
+--            : Mamta Ramendra Shukla <mamta.ramendra.shukla@cern.ch>
+--            : Javier D. Garcia <jgarcia@gl-research.com>
+-- Company    : Nikhef, CERN
+-- Created    : 2021-06-27
+-- Last update: 2021-06-27
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level file for Tandem Boot for SPEC7.
+--              See also EMPIR 17IND14 WRITE Project (http://empir.npl.co.uk/write/)
+--
+-- This Tandem Boot design is a bare minimal PCIe core that enables early
+-- PCIe enumeration for the SPEC7 by providing a Tandem PROM mode boot design
+-- that reserves the appropriated BAR sizes for SPEC7 designs based on the
+-- non Tandem capable Xilinx XDMA core that are loaded afterwards.
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2021 Nikhef, CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity spec7_tandem_boot_top is
+  port (
+    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+    DDR_cas_n : inout STD_LOGIC;
+    DDR_ck_n : inout STD_LOGIC;
+    DDR_ck_p : inout STD_LOGIC;
+    DDR_cke : inout STD_LOGIC;
+    DDR_cs_n : inout STD_LOGIC;
+    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_odt : inout STD_LOGIC;
+    DDR_ras_n : inout STD_LOGIC;
+    DDR_reset_n : inout STD_LOGIC;
+    DDR_we_n : inout STD_LOGIC;
+    FIXED_IO_ddr_vrn : inout STD_LOGIC;
+    FIXED_IO_ddr_vrp : inout STD_LOGIC;
+    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+    FIXED_IO_ps_clk : inout STD_LOGIC;
+    FIXED_IO_ps_porb : inout STD_LOGIC;
+    FIXED_IO_ps_srstb : inout STD_LOGIC;
+    pci_clk_n : in STD_LOGIC_VECTOR ( 0 to 0 );
+    pci_clk_p : in STD_LOGIC_VECTOR ( 0 to 0 );
+    perst_n : in STD_LOGIC;
+    rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+end spec7_tandem_boot_top;
+
+architecture STRUCTURE of spec7_tandem_boot_top is
+  component processing_system_pcie_tandem_boot_wrapper is
+  port (
+    pci_clk_n : in STD_LOGIC_VECTOR ( 0 to 0 );
+    pci_clk_p : in STD_LOGIC_VECTOR ( 0 to 0 );
+    perst_n : in STD_LOGIC;
+    rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    DDR_cas_n : inout STD_LOGIC;
+    DDR_cke : inout STD_LOGIC;
+    DDR_ck_n : inout STD_LOGIC;
+    DDR_ck_p : inout STD_LOGIC;
+    DDR_cs_n : inout STD_LOGIC;
+    DDR_reset_n : inout STD_LOGIC;
+    DDR_odt : inout STD_LOGIC;
+    DDR_ras_n : inout STD_LOGIC;
+    DDR_we_n : inout STD_LOGIC;
+    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+    FIXED_IO_ddr_vrn : inout STD_LOGIC;
+    FIXED_IO_ddr_vrp : inout STD_LOGIC;
+    FIXED_IO_ps_srstb : inout STD_LOGIC;
+    FIXED_IO_ps_clk : inout STD_LOGIC;
+    FIXED_IO_ps_porb : inout STD_LOGIC
+  );
+  end component processing_system_pcie_tandem_boot_wrapper;
+begin
+processing_system_pcie_tandem_boot_wrapper_i: component processing_system_pcie_tandem_boot_wrapper
+     port map (
+      DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
+      DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
+      DDR_cas_n => DDR_cas_n,
+      DDR_ck_n => DDR_ck_n,
+      DDR_ck_p => DDR_ck_p,
+      DDR_cke => DDR_cke,
+      DDR_cs_n => DDR_cs_n,
+      DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
+      DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
+      DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
+      DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
+      DDR_odt => DDR_odt,
+      DDR_ras_n => DDR_ras_n,
+      DDR_reset_n => DDR_reset_n,
+      DDR_we_n => DDR_we_n,
+      FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
+      FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
+      FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
+      FIXED_IO_ps_clk => FIXED_IO_ps_clk,
+      FIXED_IO_ps_porb => FIXED_IO_ps_porb,
+      FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
+      pci_clk_n(0) => pci_clk_n(0),
+      pci_clk_p(0) => pci_clk_p(0),
+      perst_n => perst_n,
+      rxn(1 downto 0) => rxn(1 downto 0),
+      rxp(1 downto 0) => rxp(1 downto 0),
+      txn(1 downto 0) => txn(1 downto 0),
+      txp(1 downto 0) => txp(1 downto 0)
+    );
+end STRUCTURE;
--- a/hdl/top/spec7_tandem_boot/spec7_tandem_boot_top.xdc
+++ b/hdl/top/spec7_tandem_boot/spec7_tandem_boot_top.xdc
+#   ---------------------------------------------------------------------------`
+#   -- Clocks/resets
+#   ---------------------------------------------------------------------------
+
+# Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
+#set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
+
+#   ---------------------------------------------------------------------------
+#   -- PCIe 
+#   ---------------------------------------------------------------------------
+# Bank 112 (GTX2)
+set_property PACKAGE_PIN AB3 [get_ports {rxn[0]}]
+set_property PACKAGE_PIN AB4 [get_ports {rxp[0]}]
+set_property PACKAGE_PIN AA1 [get_ports {txn[0]}]
+set_property PACKAGE_PIN AA2 [get_ports {txp[0]}]
+
+set_property PACKAGE_PIN Y3 [get_ports {rxn[1]}]
+set_property PACKAGE_PIN Y4 [get_ports {rxp[1]}]
+set_property PACKAGE_PIN W1 [get_ports {txn[1]}]
+set_property PACKAGE_PIN W2 [get_ports {txp[1]}]
+
+set_property PACKAGE_PIN R6 [get_ports pci_clk_p]
+set_property PACKAGE_PIN R5 [get_ports pci_clk_n]
+create_clock -period 10.000 -name pci_clk_p [get_ports pci_clk_p]
+
+set_property PACKAGE_PIN D13 [get_ports perst_n]
+set_property IOSTANDARD LVCMOS18 [get_ports perst_n]