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SPEC7
Commit dd89e81a authored by Pascal Bos's avatar Pascal Bos Committed by Peter Jansweijer
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Initial commit on IRIG_B capable spec7. LA32 is now IRIG_B output. 

Fixed an actual crucial bug, long PPS dutycycles hold statemachine
Made irig_b toggle-able by setting top-level generic.
parent cf879cf9
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    hdl/board/wr_spec7_pkg.vhd
    View file @ dd89e81a
    ......@@ -155,6 +155,21 @@ package wr_spec7_pkg is
    link_ok_o : out std_logic);
    end component xwrc_board_spec7;
    component wr_irigb_conv is
    generic(
    clk_freq : natural := 125000000
    );
    Port (
    clk_i : in std_logic;
    rst_n_i : in std_logic;
    pps_i : in std_logic;
    irig_b_o : out std_logic;
    irig_b_ctrl_i : in std_logic_vector(17 downto 0) := (others => '0');
    tm_time_valid_i : in std_logic;
    tm_tai_i : in std_logic_vector(39 downto 0)
    );
    end component;
    component ps_pcie_wrapper is
    port (
    aclk1_0 : in STD_LOGIC;
    ......
    hdl/ip/ip/bcd_divider/bcd_divider.xci 0 → 100644
    View file @ dd89e81a
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    olve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;m_axis_dout_tdata&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;23&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;m_axis_dout_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;aclk_intf&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXIS_DIVIDEND:S_AXIS_DIVISOR:M_AXIS_DOUT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permi
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    ,{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;
    0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;s_axis_dividend_tdata&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;15&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;s_axis_dividend_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;s_axis_dividend_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
    </xilinx:boundaryDescriptionInfo>
    </xilinx:componentInstanceExtensions>
    </spirit:vendorExtensions>
    </spirit:componentInstance>
    </spirit:componentInstances>
    </spirit:design>
    hdl/ip/ip/tai_divider/tai_divider.xci 0 → 100644
    View file @ dd89e81a
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    ission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_CLKEN&quot;:[{&quot;value&quot;:&quot;aclken&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;1000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;aresetn_intf&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:
    &quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;aclken_intf&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clockenable:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clockenable_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{}},&quot;S_AXIS_DIVISOR&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;3&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;
    :&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;val
    ue&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;s_axis_divisor_tdata&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;23&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;s_axis_divisor_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;s_axis_divisor_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;S_AXIS_DIVIDEND&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;5&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;}
    ,{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;
    0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;s_axis_dividend_tdata&quot;,&quot;physical_left&quot;:&quot;39&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;39&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;s_axis_dividend_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;s_axis_dividend_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
    </xilinx:boundaryDescriptionInfo>
    </xilinx:componentInstanceExtensions>
    </spirit:vendorExtensions>
    </spirit:componentInstance>
    </spirit:componentInstances>
    </spirit:design>
    hdl/syn/spec7_ref_design/proj_file_list.txt
    View file @ dd89e81a
    ......@@ -6,6 +6,7 @@
    #../../top/spec7_ref_design/spec7_wr_ref_top.xdc
    #../../top/spec7_ref_design/spec7_wr_hpsec_top.xdc
    ../../top/spec7_ref_design/wr_irigb_conv.vhd
    ../../top/spec7_ref_design/pll_62m5_500m.vhd
    ../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
    ../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
    ......@@ -176,6 +177,8 @@
    # bmm not supported by hdlmake? Need to add it manually...
    ../../ip/ps_pcie.bd
    ../../ip/ip/bcd_divider/bcd_divider.xci
    ../../ip/ip/tai_divider/tai_divider.xci
    ../../top/spec7_ref_design/spec7_wr_ref_top.bmm
    # include hardware version ID un FPGA USER_ID register:
    ......
    hdl/syn/spec7_ref_design/proj_properties.tcl
    View file @ dd89e81a
    ......@@ -42,6 +42,13 @@ set pps_in "single"
    #set refclk_tune_pos_slope FALSE
    # ====================================================
    # ====================================================
    # ENABLE IRIG_B OUTPUT (DEFAULT FALSE):
    # ====================================================
    # Uncomment the line below to enable IRIG_B on LA32
    #set irig_b_enable TRUE
    # ====================================================
    # Translate True/False into boolean values 1'b1, 1'b0, that are accepted by Vivado
    set vivbool_refclk_tune_pos_slope 1'b1
    if [info exists refclk_tune_pos_slope] {
    ......@@ -49,6 +56,12 @@ if [info exists refclk_tune_pos_slope] {
    set vivbool_refclk_tune_pos_slope 1'b0
    }
    }
    set vivbool_irig_b_enable 1'b0
    if [info exists irig_b_enable] {
    if ($irig_b_enable) {
    set vivbool_irig_b_enable 1'b1
    }
    }
    set proj_name spec7_wr_ref_top
    set proj_dir work
    ......@@ -64,5 +77,6 @@ if {$argc == 0 || $argv != "no_update_revision"} {
    set generics "g_design=$spec7_design \
    g_use_pps_in=$pps_in \
    g_dpram_initf=$lm32_wrpc_initf \
    g_refclk_tune_pos_slope=$vivbool_refclk_tune_pos_slope"
    g_refclk_tune_pos_slope=$vivbool_refclk_tune_pos_slope \
    g_irig_b_enable=$vivbool_irig_b_enable"
    }
    hdl/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
    View file @ dd89e81a
    ......@@ -624,11 +624,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
    #set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
    set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
    set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_p]
    #set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
    set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
    set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_n]
    #set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
    set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
    ......
    hdl/top/spec7_ref_design/spec7_wr_hpsec_top_v2.xdc
    View file @ dd89e81a
    ......@@ -624,11 +624,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
    #set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
    set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
    set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_p]
    #set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
    set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
    set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_n]
    #set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
    set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
    View file @ dd89e81a
    ......@@ -81,7 +81,8 @@ entity spec7_wr_ref_top is
    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
    g_simulation : integer := 0;
    g_use_pps_in : string := "single";
    g_refclk_tune_pos_slope : boolean := TRUE
    g_refclk_tune_pos_slope : boolean := TRUE;
    g_irig_b_enable : boolean := FALSE
    );
    port (
    ---------------------------------------------------------------------------`
    ......@@ -404,7 +405,12 @@ architecture top of spec7_wr_ref_top is
    signal m_axil_o : t_axi4_lite_master_out_32;
    signal araddr : std_logic_vector(31 downto 0);
    signal awaddr : std_logic_vector(31 downto 0);
    --TAI
    signal tm_time_valid : std_logic;
    signal tm_tai : std_logic_vector(39 downto 0);
    signal irigb : std_logic;
    --Wishbone
    signal wb_master_i : t_wishbone_master_in;
    signal wb_master_o : t_wishbone_master_out;
    ......@@ -534,6 +540,31 @@ AXI2WB : xwb_axi4lite_bridge
    wb_master_i => wb_master_i
    );
    -----------------------------------------------------------------------------
    -- Irig_B converter
    -----------------------------------------------------------------------------
    gen_irig_b : if (g_irig_b_enable = TRUE) generate
    IRIG_B : wr_irigb_conv
    generic map(
    clk_freq => 62500000
    )
    port map(
    clk_i => clk_sys_62m5,
    rst_n_i => reset_n_i,
    pps_i => wrc_pps_out,
    irig_b_o => irigb,
    tm_time_valid_i => tm_time_valid,
    tm_tai_i => tm_tai
    );
    IRIG_B_BUF : OBUFDS
    port map (
    I => irigb,
    O => fmc_la32_p,
    OB => fmc_la32_n
    );
    end generate gen_irig_b;
    -----------------------------------------------------------------------------
    -- The WR PTP core board package (WB Slave + WB Master)
    -----------------------------------------------------------------------------
    ......@@ -609,6 +640,12 @@ AXI2WB : xwb_axi4lite_bridge
    abscal_txts_o => wrc_abscal_txts_out,
    abscal_rxts_o => wrc_abscal_rxts_out,
    -- TAI
    tm_link_up_o => open,
    tm_time_valid_o => tm_time_valid,
    tm_tai_o => tm_tai,
    tm_cycles_o => open,
    pps_ext_i => wrc_pps_in,
    pps_p_o => wrc_pps_out,
    pps_led_o => wrc_pps_led,
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc
    View file @ dd89e81a
    ......@@ -619,11 +619,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
    #set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
    set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
    set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_p]
    #set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
    set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
    set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_n]
    #set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
    set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc
    View file @ dd89e81a
    ......@@ -619,11 +619,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
    #set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
    set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
    set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_p]
    #set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
    set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
    set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_n]
    #set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
    # Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
    set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
    ......
    hdl/top/spec7_ref_design/wr_irigb_conv.vhd 0 → 100644
    View file @ dd89e81a
    -------------------------------------------------------------------------------
    -- Title : White Rabbit TAI to IRIG_B converter
    -- : based on ZYNQ Z030/Z035/Z045
    -- Project : ET Pathfinder
    -- URL : https://gitlab.nikhef.nl/bosp/wr_irig_b
    -------------------------------------------------------------------------------
    -- File : wr_irigb_conf.vhd
    -- Author(s) : Pascal Bos <bosp@nikhef.nl>
    -- Company : Nikhef
    -- Created : 2021-04-29
    -- Last update: 2021-05-04
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Description: A module that takes the TAI signal from white rabbit and
    -- converts it into IRIG_B data. The PR signal is in sync with the PPS.
    --
    -------------------------------------------------------------------------------
    -- Copyright (c) 2021 Nikhef
    -------------------------------------------------------------------------------
    -- GNU LESSER GENERAL PUBLIC LICENSE
    --
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    --
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    --
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- from http://www.gnu.org/licenses/lgpl-2.1.html
    --
    -------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use ieee.numeric_std.all;
    entity wr_irigb_conv is
    generic(
    clk_freq : natural := 125000000
    );
    Port (
    clk_i : in std_logic;
    rst_n_i : in std_logic;
    pps_i : in std_logic;
    irig_b_o : out std_logic;
    irig_b_ctrl_i : in std_logic_vector(17 downto 0) := (others => '0');
    tm_time_valid_i : in std_logic;
    tm_tai_i : in std_logic_vector(39 downto 0)
    );
    end wr_irigb_conv;
    architecture Behavioral of wr_irigb_conv is
    signal tai_time_s : std_logic_vector(39 downto 0);
    signal irig_b_ctrl_s : std_logic_vector(17 downto 0);
    signal pps_reg : std_logic;
    signal pps_trigger : std_logic;
    type state_type_irig is (IDLE, PR,SEC,P1,MIN,P2,HOUR,P3,DAY_L,P4,DAY_H,P5,YEAR,P6,CTRL_1,P7,CTRL_2,P8,SBS_L,P9,SBS_H,P0,WAIT_FOR_PPS);
    signal prs,nxt : state_type_irig;
    type divisors_type is array(0 to 4) of std_logic_vector(23 downto 0);
    type divideds_type is array(0 to 4) of std_logic_vector(39 downto 0);
    type quotients_type is array(0 to 4) of std_logic_vector(39 downto 0);
    type remainders_type is array(0 to 4) of std_logic_vector(19 downto 0);
    constant divisors : divisors_type := (x"00003c", --60 seconds in minute
    x"00003c", --60 minutes in hour
    x"000018", --24 hours in day
    x"0005b5", --365.25*4 days in 4 years
    x"015180"); --seconds in a day
    signal divideds : divideds_type;
    signal quotients : quotients_type;
    signal remainders : remainders_type;
    signal divider_pipe_valids : std_logic_vector(0 to 5);
    signal start_dividers : std_logic;
    signal seconds : std_logic_vector(5 downto 0);
    signal minutes : std_logic_vector(5 downto 0);
    signal hours : std_logic_vector(3 downto 0);
    signal days : std_logic_vector(8 downto 0);
    signal years : std_logic_vector(39 downto 0); --should outlast the sun
    signal sbs : std_logic_vector(17 downto 0);
    signal enable_bcd_conv : std_logic;
    --all bcd signals are 4bits * amount * of digits + 1 index marker
    signal seconds_bcd : std_logic_vector(7 downto 0);
    signal minutes_bcd : std_logic_vector(8 downto 0);
    signal hours_bcd : std_logic_vector(8 downto 0);
    signal days_bcd : std_logic_vector(17 downto 0);
    signal years_bcd : std_logic_vector(8 downto 0);
    signal days_bcd_tdata_2 : std_logic_vector(23 downto 0);
    signal years_bcd_tdata : std_logic_vector(23 DOWNTO 0);
    signal days_bcd_tdata_1 : std_logic_vector(23 downto 0);
    signal hours_bcd_tdata : std_logic_vector(23 DOWNTO 0);
    signal seconds_bcd_tdata : std_logic_vector(23 DOWNTO 0);
    signal minutes_bcd_tdata : std_logic_vector(23 DOWNTO 0);
    signal days_bcd_valid_1 : std_logic;
    signal bcd_ready : std_logic;
    type irig_signal_type is (ONE, ZERO, MARK);
    signal irig_sig : irig_signal_type;
    signal irig_counter_enable : std_logic;
    signal irig_bit_comp : std_logic;
    signal irig_word_cnt : integer range 0 to 8;
    constant bit_time : integer := clk_freq/100;
    constant zero_time : natural := bit_time / 5;
    constant one_time : natural := bit_time / 2;
    constant mark_time : natural := bit_time - zero_time;
    signal irig_cnt : integer range 0 to bit_time;
    COMPONENT tai_divider
    PORT (
    aclk : IN STD_LOGIC;
    s_axis_divisor_tvalid : IN STD_LOGIC;
    s_axis_divisor_tready : OUT STD_LOGIC;
    s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
    s_axis_dividend_tvalid : IN STD_LOGIC;
    s_axis_dividend_tready : OUT STD_LOGIC;
    s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
    m_axis_dout_tvalid : OUT STD_LOGIC;
    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
    );
    END COMPONENT;
    COMPONENT bcd_divider
    PORT (
    aclk : IN STD_LOGIC;
    s_axis_divisor_tvalid : IN STD_LOGIC;
    s_axis_divisor_tready : OUT STD_LOGIC;
    s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    s_axis_dividend_tvalid : IN STD_LOGIC;
    s_axis_dividend_tready : OUT STD_LOGIC;
    s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    m_axis_dout_tvalid : OUT STD_LOGIC;
    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
    );
    END COMPONENT;
    begin
    --
    -- This process latches the tai_time when its valid and starts the divider --
    --
    tai_register : process (clk_i, rst_n_i ) is
    begin
    if rst_n_i = '0' then
    tai_time_s <= (others => '0');
    start_dividers <= '0';
    elsif rising_edge(clk_i) then
    if tm_time_valid_i = '1' then
    tai_time_s <= tm_tai_i;
    start_dividers <= '1';
    else
    start_dividers <= '0';
    end if;
    end if;
    end process tai_register;
    ctrl_register : process (clk_i, rst_n_i ) is
    begin
    if rst_n_i = '0' then
    irig_b_ctrl_s <= (others => '0');
    elsif rising_edge(clk_i) then
    if pps_i = '1' then
    irig_b_ctrl_s <= irig_b_ctrl_i;
    end if;
    end if;
    end process ctrl_register;
    pps_register : process (clk_i, rst_n_i ) is
    begin
    if rst_n_i = '0' then
    pps_reg <= '0';
    elsif rising_edge(clk_i) then
    pps_reg <= pps_i;
    end if;
    end process pps_register;
    pps_trigger <= '1' when pps_i = '1' and pps_reg = '0' else '0';
    --
    -- this statement generates the 5 dividers for: Seconds&Minutes, Hours, Days, Years and SBS --
    -- it utilizes both the dividers "Answer/Quotient" and "Remainder", as can be seen below --
    --
    -- ___________ ___________ ___________ _________________ ___________
    -- --------->| |---------------| |---------------| |---------------|shift 2bits left |----| |--------[current year since 1970]
    -- Tai_Time | DIVIDE BY |(Answer) | DIVIDE BY |(Answer) | DIVIDE BY |(Answer) | (Multiply by 4) | | DIVIDE BY |(Answer)
    -- (seconds) | 60 | | 60 | | 24 | |_________________| | 1425 |
    -- | |------------ | |------------ | |------------ | |------------
    -- | |(Remainder) | | |(Remainder) | | |(Remainder) | | |(Remainder) |
    -- |___________| | |___________| | |___________| | |___________| |
    -- V V V V
    -- [seconds in the current minute] [minutes in the current hour] [Hour in the current day] [Day in the current year - 1]
    --
    --
    gen_tai_dividers : for I in 0 to 4 generate
    signal answer : std_logic_vector(63 downto 0);
    begin
    divider_inst : tai_divider
    PORT MAP (
    aclk => clk_i,
    s_axis_divisor_tvalid => divider_pipe_valids(I),
    s_axis_divisor_tready => open,
    s_axis_divisor_tdata => divisors(I),
    s_axis_dividend_tvalid => divider_pipe_valids(I),
    s_axis_dividend_tready => open,
    s_axis_dividend_tdata => divideds(I),
    m_axis_dout_tvalid => divider_pipe_valids(I+1),
    m_axis_dout_tdata => answer
    );
    quotients(I) <= answer(63 downto 24);
    remainders(I) <= answer(19 downto 0);
    end generate gen_tai_dividers;
    divider_pipe_valids(0) <= start_dividers;
    divideds(0) <= tai_time_s;
    divideds(1) <= quotients(0); -- quotient of seconds will be divided by 60 to get minutes
    divideds(2) <= quotients(1); -- quotient of minutes will be divided by 24 to get hours
    divideds(3) <= quotients(2)(37 downto 0) & "00"; -- quotient of hours will be multiplied by 4 and divided by 4 years to get 4 times the days
    divideds(4) <= tai_time_s;
    --latches the output of all dividers after the final dividers have finished (could be cleaner, for now it works)
    --starts the bcd_dividers
    date_register : process (clk_i, rst_n_i) is
    begin
    if rst_n_i = '0' then
    seconds <= (others => '0');
    minutes <= (others => '0');
    hours <= (others => '0');
    days <= (others => '0');
    years <= (others => '0');
    sbs <= (others => '0');
    enable_bcd_conv <= '0';
    elsif rising_edge(clk_i) then
    if divider_pipe_valids(5) = '1' then
    seconds <= remainders(0)(5 downto 0);
    minutes <= remainders(1)(5 downto 0);
    hours <= remainders(2)(3 downto 0);
    days <= std_logic_vector(unsigned(remainders(3)(10 downto 2)) + 1); --there is no day zero
    years <= quotients(3);
    sbs(16 downto 0) <= remainders(4)(16 downto 0);
    sbs(17) <= '0';
    enable_bcd_conv <= '1';
    else
    enable_bcd_conv <= '0';
    end if;
    end if;
    end process date_register;
    --counts the clock cycles in each irig bit
    irig_counter : process (clk_i, rst_n_i) is
    begin
    if rst_n_i = '0' then
    irig_cnt <= 0;
    elsif rising_edge(clk_i) then
    if prs = IDLE or prs = WAIT_FOR_PPS then
    irig_cnt <= 1; --when a pps is seen it starts from one to compensate for that clock cycle
    elsif irig_cnt = bit_time-1 then
    irig_cnt <= 0;
    else
    irig_cnt <= irig_cnt + 1;
    end if;
    end if;
    end process irig_counter;
    irig_bit_comp <= '1' when irig_cnt = bit_time-1 else '0';
    --the driver of the irig_b outbut signal
    --this is combinatoric to ensure a same-clock cycle start with the pps.
    irig_b_o <= pps_i when (prs = IDLE or prs = WAIT_FOR_PPS)
    else '0' when (rst_n_i = '0')
    or (irig_cnt > mark_time)
    or (irig_cnt > one_time and irig_sig = ONE)
    or (irig_cnt > zero_time and irig_sig = ZERO)
    else '1';
    --counts its position within the current irig_b word ( f.e.: 1,2,4,8,10,20,40)
    word_counter : process (clk_i, rst_n_i) is
    begin
    if rst_n_i = '0' then
    irig_word_cnt <= 0;
    elsif rising_edge(clk_i) then
    if prs /= nxt then
    irig_word_cnt <= 0;
    elsif irig_bit_comp = '1' then
    irig_word_cnt <= irig_word_cnt + 1;
    end if;
    end if;
    end process word_counter;
    --State machine, a three process Moore model. AS IT SHOULD BE!
    state_register : process (clk_i, rst_n_i) is
    begin
    if rst_n_i = '0' then
    prs <= IDLE;
    elsif rising_edge(clk_i) then
    prs <= nxt;
    end if;
    end process state_register;
    next_state_decoder : process(prs,rst_n_i,pps_trigger,irig_word_cnt,irig_bit_comp,irig_cnt) is
    begin
    if rst_n_i = '0' then
    nxt <= IDLE;
    elsif pps_trigger = '1' then --A PPS signal will ALWAYS result in a new frame being send.
    nxt <= PR;
    else
    case prs is
    when IDLE =>
    nxt <= IDLE; -- stay here until pps_trigger jumps to PR.
    when PR =>
    if irig_bit_comp = '1' then
    nxt <= SEC;
    else
    nxt <= PR;
    end if;
    when SEC =>
    if irig_word_cnt >= 7 and irig_bit_comp = '1' then --checks if the last bit has been send
    nxt <= P1;
    else
    nxt <= SEC;
    end if;
    when P1 =>
    if irig_bit_comp = '1' then
    nxt <= MIN;
    else
    nxt <= P1;
    end if;
    when MIN =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P2;
    else
    nxt <= MIN;
    end if;
    when P2 =>
    if irig_bit_comp = '1' then
    nxt <= HOUR;
    else
    nxt <= P2;
    end if;
    when HOUR =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P3;
    else
    nxt <= HOUR;
    end if;
    when P3 =>
    if irig_bit_comp = '1' then
    nxt <= DAY_L;
    else
    nxt <= P3;
    end if;
    when DAY_L =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P4;
    else
    nxt <= DAY_L;
    end if;
    when P4 =>
    if irig_bit_comp = '1' then
    nxt <= DAY_H;
    else
    nxt <= P4;
    end if;
    when DAY_H =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P5;
    else
    nxt <= DAY_H;
    end if;
    when P5 =>
    if irig_bit_comp = '1' then
    nxt <= YEAR;
    else
    nxt <= P5;
    end if;
    when YEAR =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P6;
    else
    nxt <= YEAR;
    end if;
    when P6 =>
    if irig_bit_comp = '1' then
    nxt <= CTRL_1;
    else
    nxt <= P6;
    end if;
    when CTRL_1 =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P7;
    else
    nxt <= CTRL_1;
    end if;
    when P7 =>
    if irig_bit_comp = '1' then
    nxt <= CTRL_2;
    else
    nxt <= P7;
    end if;
    when CTRL_2 =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P8;
    else
    nxt <= CTRL_2;
    end if;
    when P8 =>
    if irig_bit_comp = '1' then
    nxt <= SBS_L;
    else
    nxt <= P8;
    end if;
    when SBS_L =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P9;
    else
    nxt <= SBS_L;
    end if;
    when P9 =>
    if irig_bit_comp = '1' then
    nxt <= SBS_H;
    else
    nxt <= P9;
    end if;
    when SBS_H =>
    if irig_word_cnt >= 8 and irig_bit_comp = '1' then
    nxt <= P0;
    else
    nxt <= SBS_H;
    end if;
    when P0 =>
    if irig_cnt > mark_time then
    nxt <= WAIT_FOR_PPS;
    else
    nxt <= P0;
    end if;
    when WAIT_FOR_PPS =>
    nxt <= WAIT_FOR_PPS; -- stay here until pps_trigger jumps to PR.
    end case;
    end if;
    end process next_state_decoder;
    output_decoder : process(prs, irig_word_cnt, seconds_bcd, minutes_bcd, hours_bcd, days_bcd, years_bcd, irig_b_ctrl_s, sbs) is
    variable irig_bit : std_logic;
    variable irig_mark : std_logic;
    begin
    irig_mark := '0';
    irig_bit := '0';
    case prs is
    when IDLE | PR | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P0 | WAIT_FOR_PPS =>
    irig_mark := '1'; -- All these states are MARK signals.
    when SEC =>
    irig_bit := seconds_bcd(irig_word_cnt);
    when MIN =>
    irig_bit := minutes_bcd(irig_word_cnt);
    when HOUR =>
    irig_bit := hours_bcd(irig_word_cnt);
    when DAY_L =>
    irig_bit := days_bcd(irig_word_cnt);
    when DAY_H =>
    irig_bit := days_bcd(irig_word_cnt+9);
    when YEAR =>
    irig_bit := years_bcd(irig_word_cnt);
    when CTRL_1 =>
    irig_bit := irig_b_ctrl_s(irig_word_cnt);
    when CTRL_2 =>
    irig_bit := irig_b_ctrl_s(irig_word_cnt+9);
    when SBS_L =>
    irig_bit := sbs(irig_word_cnt);
    when SBS_H =>
    irig_bit := sbs(irig_word_cnt+9);
    end case;
    if irig_mark = '1' then
    irig_sig <= MARK;
    elsif irig_bit = '1' then
    irig_sig <= ONE;
    else
    irig_sig <= ZERO;
    end if;
    end process output_decoder;
    --The divide-by-ten dividers to convert binary values into bcd values
    -- ___________
    -- --------->| |---------> 4
    -- Value | DIVIDE BY | (Answer)
    -- (binary) | 10 |
    -- [f.e: 42] | |---------> 2
    -- | | (Remainder)
    -- |___________|
    --
    --The diveder for "days" has an additional divide-by-100 divider because there are more then 99 days in a year.
    seconds_bcd_divider : bcd_divider
    PORT MAP (
    aclk => clk_i,
    s_axis_divisor_tvalid => enable_bcd_conv,
    s_axis_divisor_tready => open,
    s_axis_divisor_tdata => x"0A", --divides by 10
    s_axis_dividend_tvalid => enable_bcd_conv,
    s_axis_dividend_tready => open,
    s_axis_dividend_tdata(15 downto 6) => (others => '0'),
    s_axis_dividend_tdata(5 downto 0) => seconds,
    m_axis_dout_tvalid => open,
    m_axis_dout_tdata => seconds_bcd_tdata
    );
    --all the bcd data has some '0' inserted between then to separate decimal and unit, as is requierd by IRIG
    seconds_bcd <= seconds_bcd_tdata(10 downto 8) & '0' & seconds_bcd_tdata(3 downto 0);
    minutes_bcd_divider : bcd_divider
    PORT MAP (
    aclk => clk_i,
    s_axis_divisor_tvalid => enable_bcd_conv,
    s_axis_divisor_tready => open,
    s_axis_divisor_tdata => x"0A",
    s_axis_dividend_tvalid => enable_bcd_conv,
    s_axis_dividend_tready => open,
    s_axis_dividend_tdata(15 downto 6) => (others => '0'),
    s_axis_dividend_tdata(5 downto 0) => minutes,
    m_axis_dout_tvalid => open,
    m_axis_dout_tdata => minutes_bcd_tdata
    );
    minutes_bcd <= '0' & minutes_bcd_tdata(10 downto 8) & '0' & minutes_bcd_tdata(3 downto 0);
    hours_bcd_divider : bcd_divider
    PORT MAP (
    aclk => clk_i,
    s_axis_divisor_tvalid => enable_bcd_conv,
    s_axis_divisor_tready => open,
    s_axis_divisor_tdata => x"0A",
    s_axis_dividend_tvalid => enable_bcd_conv,
    s_axis_dividend_tready => open,
    s_axis_dividend_tdata(15 downto 4) => (others => '0'),
    s_axis_dividend_tdata(3 downto 0) => hours,
    m_axis_dout_tvalid => open,
    m_axis_dout_tdata => hours_bcd_tdata
    );
    hours_bcd <= "00" & hours_bcd_tdata(9 downto 8) & '0' & hours_bcd_tdata(3 downto 0);
    years_bcd_divider : bcd_divider
    PORT MAP (
    aclk => clk_i,
    s_axis_divisor_tvalid => enable_bcd_conv,
    s_axis_divisor_tready => open,
    s_axis_divisor_tdata => x"0A",
    s_axis_dividend_tvalid => enable_bcd_conv,
    s_axis_dividend_tready => open,
    s_axis_dividend_tdata => years(15 downto 0),
    m_axis_dout_tvalid => open,
    m_axis_dout_tdata => years_bcd_tdata
    );
    years_bcd <= years_bcd_tdata(11 downto 8) & '0' & years_bcd_tdata(3 downto 0);
    days_bcd_divider_1 : bcd_divider
    PORT MAP (
    aclk => clk_i,
    s_axis_divisor_tvalid => enable_bcd_conv,
    s_axis_divisor_tready => open,
    s_axis_divisor_tdata => x"64", --100
    s_axis_dividend_tvalid => enable_bcd_conv,
    s_axis_dividend_tready => open,
    s_axis_dividend_tdata(15 downto 9) => (others => '0'),
    s_axis_dividend_tdata(8 downto 0) => days,
    m_axis_dout_tvalid => days_bcd_valid_1,
    m_axis_dout_tdata => days_bcd_tdata_2
    );
    days_bcd_divider_2 : bcd_divider
    PORT MAP (
    aclk => clk_i,
    s_axis_divisor_tvalid => days_bcd_valid_1,
    s_axis_divisor_tready => open,
    s_axis_divisor_tdata => x"0A",
    s_axis_dividend_tvalid => days_bcd_valid_1,
    s_axis_dividend_tready => open,
    s_axis_dividend_tdata(15 downto 8) => (others => '0'),
    s_axis_dividend_tdata(7 downto 0) => days_bcd_tdata_2(7 downto 0),
    m_axis_dout_tvalid => bcd_ready,
    m_axis_dout_tdata => days_bcd_tdata_1
    );
    days_bcd <= "0000000" & days_bcd_tdata_2(9 downto 8) & days_bcd_tdata_1(11 downto 8) & '0' & days_bcd_tdata_1(3 downto 0);
    end Behavioral;
    sw/scripts/viv_do_all.tcl
    View file @ dd89e81a
    ......@@ -208,6 +208,11 @@ if [info exists refclk_tune_pos_slope] {
    puts $git_log_fp "reference oscillator negative tune slope"
    }
    }
    if [info exists irig_b_enable] {
    if ($irig_b_enable) {
    puts $git_log_fp "IRIG-B module implemented"
    }
    }
    puts $git_log_fp "Build was based on the following SHA codes:"
    puts $git_log_fp "spec7.git $spec7_sha"
    puts $git_log_fp "wr-cores.git $wr_cores_sha"
    ......
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