Commit dd89e81a authored by Pascal Bos's avatar Pascal Bos Committed by Peter Jansweijer

Initial commit on IRIG_B capable spec7. LA32 is now IRIG_B output.

Fixed an actual crucial bug, long PPS dutycycles hold statemachine
Made irig_b toggle-able by setting top-level generic.
parent cf879cf9
Pipeline #3255 failed with stage
in 2 minutes and 7 seconds
......@@ -155,6 +155,21 @@ package wr_spec7_pkg is
link_ok_o : out std_logic);
end component xwrc_board_spec7;
component wr_irigb_conv is
generic(
clk_freq : natural := 125000000
);
Port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pps_i : in std_logic;
irig_b_o : out std_logic;
irig_b_ctrl_i : in std_logic_vector(17 downto 0) := (others => '0');
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0)
);
end component;
component ps_pcie_wrapper is
port (
aclk1_0 : in STD_LOGIC;
......
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......@@ -6,6 +6,7 @@
#../../top/spec7_ref_design/spec7_wr_ref_top.xdc
#../../top/spec7_ref_design/spec7_wr_hpsec_top.xdc
../../top/spec7_ref_design/wr_irigb_conv.vhd
../../top/spec7_ref_design/pll_62m5_500m.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
......@@ -176,6 +177,8 @@
# bmm not supported by hdlmake? Need to add it manually...
../../ip/ps_pcie.bd
../../ip/ip/bcd_divider/bcd_divider.xci
../../ip/ip/tai_divider/tai_divider.xci
../../top/spec7_ref_design/spec7_wr_ref_top.bmm
# include hardware version ID un FPGA USER_ID register:
......
......@@ -42,6 +42,13 @@ set pps_in "single"
#set refclk_tune_pos_slope FALSE
# ====================================================
# ====================================================
# ENABLE IRIG_B OUTPUT (DEFAULT FALSE):
# ====================================================
# Uncomment the line below to enable IRIG_B on LA32
#set irig_b_enable TRUE
# ====================================================
# Translate True/False into boolean values 1'b1, 1'b0, that are accepted by Vivado
set vivbool_refclk_tune_pos_slope 1'b1
if [info exists refclk_tune_pos_slope] {
......@@ -49,6 +56,12 @@ if [info exists refclk_tune_pos_slope] {
set vivbool_refclk_tune_pos_slope 1'b0
}
}
set vivbool_irig_b_enable 1'b0
if [info exists irig_b_enable] {
if ($irig_b_enable) {
set vivbool_irig_b_enable 1'b1
}
}
set proj_name spec7_wr_ref_top
set proj_dir work
......@@ -64,5 +77,6 @@ if {$argc == 0 || $argv != "no_update_revision"} {
set generics "g_design=$spec7_design \
g_use_pps_in=$pps_in \
g_dpram_initf=$lm32_wrpc_initf \
g_refclk_tune_pos_slope=$vivbool_refclk_tune_pos_slope"
g_refclk_tune_pos_slope=$vivbool_refclk_tune_pos_slope \
g_irig_b_enable=$vivbool_irig_b_enable"
}
......@@ -624,11 +624,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
......
......@@ -624,11 +624,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
......
......@@ -81,7 +81,8 @@ entity spec7_wr_ref_top is
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0;
g_use_pps_in : string := "single";
g_refclk_tune_pos_slope : boolean := TRUE
g_refclk_tune_pos_slope : boolean := TRUE;
g_irig_b_enable : boolean := FALSE
);
port (
---------------------------------------------------------------------------`
......@@ -404,7 +405,12 @@ architecture top of spec7_wr_ref_top is
signal m_axil_o : t_axi4_lite_master_out_32;
signal araddr : std_logic_vector(31 downto 0);
signal awaddr : std_logic_vector(31 downto 0);
--TAI
signal tm_time_valid : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal irigb : std_logic;
--Wishbone
signal wb_master_i : t_wishbone_master_in;
signal wb_master_o : t_wishbone_master_out;
......@@ -534,6 +540,31 @@ AXI2WB : xwb_axi4lite_bridge
wb_master_i => wb_master_i
);
-----------------------------------------------------------------------------
-- Irig_B converter
-----------------------------------------------------------------------------
gen_irig_b : if (g_irig_b_enable = TRUE) generate
IRIG_B : wr_irigb_conv
generic map(
clk_freq => 62500000
)
port map(
clk_i => clk_sys_62m5,
rst_n_i => reset_n_i,
pps_i => wrc_pps_out,
irig_b_o => irigb,
tm_time_valid_i => tm_time_valid,
tm_tai_i => tm_tai
);
IRIG_B_BUF : OBUFDS
port map (
I => irigb,
O => fmc_la32_p,
OB => fmc_la32_n
);
end generate gen_irig_b;
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
......@@ -609,6 +640,12 @@ AXI2WB : xwb_axi4lite_bridge
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
-- TAI
tm_link_up_o => open,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => open,
pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out,
pps_led_o => wrc_pps_led,
......
......@@ -619,11 +619,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
......
......@@ -619,11 +619,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la32_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
......
This diff is collapsed.
......@@ -208,6 +208,11 @@ if [info exists refclk_tune_pos_slope] {
puts $git_log_fp "reference oscillator negative tune slope"
}
}
if [info exists irig_b_enable] {
if ($irig_b_enable) {
puts $git_log_fp "IRIG-B module implemented"
}
}
puts $git_log_fp "Build was based on the following SHA codes:"
puts $git_log_fp "spec7.git $spec7_sha"
puts $git_log_fp "wr-cores.git $wr_cores_sha"
......
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