63ea1b04 (HEAD -> spec7_proposed_master, origin/spec7_proposed_master) TX Phase timing became critical after moving to Use ODIV2 instead of a separate div2 FF
f16d10f9 (HEAD -> peter_wrpc-v5, origin/peter_wrpc-v5, origin/peter_220419e_wrpc-v5, peter_220419e_wrpc-v5) spec7 entry and spec7_defconfig in yml
1c12022f slightly wider tolerance avoids endless sampling and no link up
694d2145 add and init I2C_AUX bus (but do nothing else yet)