Skip to content

S
SPEC7
Commit c734c613 authored by Peter Jansweijer's avatar Peter Jansweijer
Browse files
Options

implement gtx_lp onto wrpc-v5

parent a5ed0a4b
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 154 additions and 148 deletions
.gitmodules
View file @ c734c613
[submodule "hdl/wr-cores"]
path = hdl/wr-cores
url = https://ohwr.org/project/wr-cores.git
branch = proposed_spec7
\ No newline at end of file
branch = peter_spec7_v5
\ No newline at end of file
hdl/spec7_ref_design/syn/proj_file_list.txt
View file @ c734c613
......@@ -2,6 +2,7 @@
# hdlmake list-files > proj_file_list.txt
../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.xdc
../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_reset.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_serial_dac.vhd
......@@ -9,10 +10,11 @@
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_register.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
......@@ -33,24 +35,22 @@
../../wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd
../../wr-cores/modules/wrc_core/wrc_diags_pkg.vhd
../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/gtx_comma_detect_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/whiterabbit_gtxe2_channel_wrapper_gt_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/axi/axi4_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
../../wr-cores/modules/fabric/wr_fabric_pkg.vhd
......@@ -73,10 +73,10 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
../../wr-cores/modules/fabric/xwrf_mux.vhd
../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
../../wr-cores/modules/timing/pulse_stamper_sync.vhd
......@@ -88,6 +88,7 @@
../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
../../wr-cores/modules/wr_streamers/ts_restore_tai.vhd
../../wr-cores/modules/wrc_core/xwrc_diags_wb.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
......@@ -102,15 +103,14 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
../../wr-cores/modules/timing/dmtd_phase_meas.vhd
../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
../../wr-cores/modules/fabric/xwb_fabric_sink.vhd
../../wr-cores/modules/fabric/xwb_fabric_source.vhd
../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd
......
hdl/spec7_write_design/syn/proj_file_list.txt
View file @ c734c613
......@@ -2,6 +2,7 @@
# hdlmake list-files > proj_file_list.txt
../../wr-cores/top/spec7_write_design/spec7_write_top.xdc
../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_reset.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_serial_dac.vhd
......@@ -9,10 +10,11 @@
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_register.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
......@@ -33,25 +35,23 @@
../../wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd
../../wr-cores/modules/wrc_core/wrc_diags_pkg.vhd
../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/gtx_comma_detect_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/whiterabbit_gtxe2_channel_wrapper_gt_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
../../wr-cores/top/spec7_write_design/pll_62m5_500m.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/axi/axi4_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
../../wr-cores/modules/fabric/wr_fabric_pkg.vhd
......@@ -76,9 +76,8 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
../../wr-cores/modules/fabric/xwrf_mux.vhd
../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
../../wr-cores/modules/timing/pulse_stamper_sync.vhd
......@@ -90,6 +89,7 @@
../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
../../wr-cores/modules/wr_streamers/ts_restore_tai.vhd
../../wr-cores/modules/wrc_core/xwrc_diags_wb.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
../../wr-cores/top/spec7_write_design/gen_10mhz.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
......@@ -105,15 +105,14 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
../../wr-cores/modules/timing/dmtd_phase_meas.vhd
../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
../../wr-cores/modules/fabric/xwb_fabric_sink.vhd
../../wr-cores/modules/fabric/xwb_fabric_source.vhd
../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd
......
wr-cores @ 54f835c0
Subproject commit fd1c3919c1d01f0a0ae77d99c66da0d5b092593b
Subproject commit 54f835c0a142ca2c255b98bf27adb72c309d0d59
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment