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SPEC7
Commit b55cc577 authored by Peter Jansweijer's avatar Peter Jansweijer
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Add selection for reference oscillator tune slope (default positive)

parent e284ea80
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Showing with 47 additions and 7 deletions
hdl/board/wr_spec7_pkg.vhd
View file @ b55cc577
......@@ -58,7 +58,8 @@ package wr_spec7_pkg is
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
g_diag_rw_size : integer := 0;
g_refclk_tune_pos_slope : boolean := TRUE);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
......
hdl/board/wrc_board_spec7.vhd
View file @ b55cc577
......@@ -75,7 +75,8 @@ entity wrc_board_spec7 is
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0
g_diag_rw_vector_width : integer := 0;
g_refclk_tune_pos_slope : boolean := TRUE
);
port (
---------------------------------------------------------------------------
......
hdl/board/xwrc_board_spec7.vhd
View file @ b55cc577
......@@ -76,7 +76,8 @@ entity xwrc_board_spec7 is
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
g_diag_rw_size : integer := 0;
g_refclk_tune_pos_slope : boolean := TRUE
);
port (
---------------------------------------------------------------------------
......@@ -304,6 +305,7 @@ architecture struct of xwrc_board_spec7 is
signal dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_refclk_load : std_logic;
signal dac_refclk_data : std_logic_vector(15 downto 0);
signal dac_refclk_data_slp : std_logic_vector(15 downto 0);
-- OneWire
signal onewire_in : std_logic_vector(1 downto 0);
......@@ -606,6 +608,18 @@ begin -- architecture struct
dac_sclk_o => dac_dmtd_sclk_o,
dac_sdata_o => dac_dmtd_din_o);
-- Default reference oscillators have positive tune slope. For negative tune slope
-- binary negate (= One's complement) the DAC value.
gen_refclk_tune_pos_slope : if (g_refclk_tune_pos_slope = TRUE)
generate
dac_refclk_data_slp <= dac_refclk_data;
end generate gen_refclk_tune_pos_slope;
gen_refclk_tune_neg_slope : if (g_refclk_tune_pos_slope = FALSE)
generate
dac_refclk_data_slp <= not dac_refclk_data;
end generate gen_refclk_tune_neg_slope;
cmp_refclk_dac : gc_serial_dac
generic map (
g_num_data_bits => 16,
......@@ -615,7 +629,7 @@ begin -- architecture struct
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_refclk_data,
value_i => dac_refclk_data_slp,
cs_sel_i => "1",
load_i => dac_refclk_load,
sclk_divsel_i => "001",
......
hdl/syn/spec7_ref_design/proj_properties.tcl
View file @ b55cc577
......@@ -35,6 +35,21 @@ set pps_in "single"
#set pps_in "diff"
# ====================================================
# ====================================================
# SELECT REFERENCE OSCILATOR TUNE SLOPE (DEFAULT TRUE):
# ====================================================
# Uncomment the line below when the reference oscillator has negative tune slope.
#set refclk_tune_pos_slope FALSE
# ====================================================
# Translate True/False into boolean values 1'b1, 1'b0, that are accepted by Vivado
set vivbool_refclk_tune_pos_slope 1'b1
if [info exists refclk_tune_pos_slope] {
if (!$refclk_tune_pos_slope) {
set vivbool_refclk_tune_pos_slope 1'b0
}
}
set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
......@@ -48,5 +63,6 @@ if {$argc == 0 || $argv != "no_update_revision"} {
set generics "g_design=$spec7_design \
g_use_pps_in=$pps_in \
g_dpram_initf=$lm32_wrpc_initf"
g_dpram_initf=$lm32_wrpc_initf \
g_refclk_tune_pos_slope=$vivbool_refclk_tune_pos_slope"
}
hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
View file @ b55cc577
......@@ -80,7 +80,8 @@ entity spec7_wr_ref_top is
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0;
g_use_pps_in : string := "single"
g_use_pps_in : string := "single";
g_refclk_tune_pos_slope : boolean := TRUE
);
port (
---------------------------------------------------------------------------`
......@@ -542,7 +543,9 @@ AXI2WB : xwb_axi4lite_bridge
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_dpram_initf,
g_fabric_iface => PLAIN)
g_fabric_iface => PLAIN,
g_refclk_tune_pos_slope => g_refclk_tune_pos_slope
)
port map (
areset_n_i => reset_n_i,
clk_125m_dmtd_n_i => clk_125m_dmtd_n_i,
......
sw/scripts/viv_do_all.tcl
View file @ b55cc577
......@@ -203,6 +203,11 @@ puts $git_log_fp "device = $device"
if [info exists pps_in] {
puts $git_log_fp "pps_in = $pps_in"
}
if [info exists refclk_tune_pos_slope] {
if (!$refclk_tune_pos_slope) {
puts $git_log_fp "reference oscillator negative tune slope"
}
}
puts $git_log_fp "Build was based on the following SHA codes:"
puts $git_log_fp "spec7.git $spec7_sha"
puts $git_log_fp "wr-cores.git $wr_cores_sha"
......
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