Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
S
SPEC7
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
5
Issues
5
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
SPEC7
Commits
b222ae5b
Commit
b222ae5b
authored
Dec 06, 2023
by
Peter Jansweijer
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
update wr-cores (containing extend DAC bit count)
parent
3637edc9
Pipeline
#5036
failed with stage
in 2 minutes and 6 seconds
Changes
3
Pipelines
1
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
10 additions
and
10 deletions
+10
-10
VCom_spec7_wr_ref_top_Functional.tcl
...sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
+5
-5
proj_file_list.txt
hdl/syn/spec7_ref_design/proj_file_list.txt
+4
-4
wr-cores
hdl/wr-cores
+1
-1
No files found.
hdl/sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
View file @
b222ae5b
...
...
@@ -6,8 +6,8 @@
#vcom -explicit -93 -work work ../../top/spec7_ref_design/spec7_wr_ref_top.xdc
#vcom -explicit -93 -work work ../../top/spec7_ref_design/spec7_wr_hpsec_top.xdc
vcom -explicit -93 -work work ../../top/spec7_ref_design/wr_irigb_conv.vhd
vcom -explicit -93 -work work ../../top/spec7_ref_design/pll_62m5_500m.vhd
vcom -explicit -93 -work work ../../top/spec7_ref_design/wr_irigb_conv.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
...
...
@@ -63,6 +63,7 @@ vlog -work work ../../wr-cores/ip_cores/urv-core/rtl/urv_regfile.v
vlog -work work ../../wr-cores/ip_cores/urv-core/rtl/urv_writeback.v
vcom -explicit -93 -work work ../../wr-cores/modules/fabric/wr_fabric_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_sampler.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_mdio_regs.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
...
...
@@ -85,7 +86,7 @@ vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wish
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vlog -work work ../../wr-cores/ip_cores/urv-core/rtl/urv_cpu.v
vcom -explicit -93 -work work ../../wr-cores/modules/fabric/xwrf_mux.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_
sampl
er.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_
with_deglitch
er.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/pulse_stamper_sync.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
...
...
@@ -95,6 +96,7 @@ vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/dropping_buffe
vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/ts_restore_tai.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd
vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd
...
...
@@ -105,17 +107,15 @@ vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wish
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_
with_deglitcher
.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_
phase_meas
.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/pulse_stamper.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/fabric/xwb_fabric_sink.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/fabric/xwb_fabric_source.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_phase_meas.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_leds_controller.vhd
...
...
hdl/syn/spec7_ref_design/proj_file_list.txt
View file @
b222ae5b
...
...
@@ -63,6 +63,7 @@
../../wr-cores/ip_cores/urv-core/rtl/urv_writeback.v
../../wr-cores/modules/fabric/wr_fabric_pkg.vhd
../../wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
../../wr-cores/modules/timing/dmtd_sampler.vhd
../../wr-cores/modules/wr_endpoint/ep_mdio_regs.vhd
../../wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd
../../wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
...
...
@@ -85,7 +86,7 @@
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
../../wr-cores/ip_cores/urv-core/rtl/urv_cpu.v
../../wr-cores/modules/fabric/xwrf_mux.vhd
../../wr-cores/modules/timing/dmtd_
sampl
er.vhd
../../wr-cores/modules/timing/dmtd_
with_deglitch
er.vhd
../../wr-cores/modules/timing/pulse_stamper_sync.vhd
../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd
../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
...
...
@@ -95,6 +96,7 @@
../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
../../wr-cores/modules/wr_streamers/ts_restore_tai.vhd
../../wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd
...
...
@@ -105,17 +107,15 @@
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
../../wr-cores/modules/timing/dmtd_
with_deglitcher
.vhd
../../wr-cores/modules/timing/dmtd_
phase_meas
.vhd
../../wr-cores/modules/timing/pulse_stamper.vhd
../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
../../wr-cores/modules/fabric/xwb_fabric_sink.vhd
../../wr-cores/modules/fabric/xwb_fabric_source.vhd
../../wr-cores/modules/timing/dmtd_phase_meas.vhd
../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd
../../wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
../../wr-cores/modules/wr_endpoint/ep_leds_controller.vhd
...
...
wr-cores
@
456b9330
Subproject commit
0e3962b4d4f8def75e2804d5b85eb183fdbea6ef
Subproject commit
456b933057ff12a827059e4a43b027f435d994e5
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment