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SPEC7
Commit 9bfc68d0 authored by Pascal Bos's avatar Pascal Bos Committed by Peter Jansweijer
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added PS in ref design, adjusted BAR addresses.

parent a5ed0a4b
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hdl/spec7_ref_design/syn/proj_file_list.txt
View file @ 9bfc68d0
......@@ -190,7 +190,7 @@
# bmm not supported by hdlmake? Need to add it manually...
../../wr-cores/platform/xilinx/wr_pcie/Pcie.tcl
../../wr-cores/platform/xilinx/wr_pcie/processing_system_pcie.tcl
../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.bmm
# include hardware version ID un FPGA USER_ID register:
......
hdl/spec7_write_design/syn/proj_file_list.txt
View file @ 9bfc68d0
......@@ -74,7 +74,6 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
......
wr-cores @ 43b3139d
Subproject commit fd1c3919c1d01f0a0ae77d99c66da0d5b092593b
Subproject commit 43b3139dfbb53de4cf723f576db661524dc1fc6a
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