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SPEC7
Commit 93fd5218 authored by Peter Jansweijer's avatar Peter Jansweijer
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Merge remote-tracking branch 'remotes/origin/peter_210601' into proposed_master

parents 0492a2df a51dea55
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.gitmodules
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[submodule "hdl/wr-cores"]
path = hdl/wr-cores
url = https://ohwr.org/project/wr-cores.git
branch = proposed_spec7
\ No newline at end of file
branch = peter_spec7_v5
\ No newline at end of file
hdl/ip/processing_system_pcie.bd 0 → 100644
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hdl/spec7_ref_design/sim/modelsim.ini
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......@@ -13,8 +13,8 @@ INIVersion = "2019.4"
[Library]
others=$VHDLLIBS/v2019.2/modelsim.ini
work = spec7.lib
work = spec7.lib
[DefineOptionset]
; Define optionset entries for the various compilers, vmake, and vsim.
; These option sets can be used with the "-optionset <optionsetname>" syntax.
......
hdl/spec7_ref_design/syn/do_vivado_mmi_elf.sh deleted 100755 → 0
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#! /bin/bash
proj_name=spec7_wr_ref_top
lm32_wrpc_elf=../../../sw/precompiled/wrps-sw_spec7/wrc.elf
lm32_wrpc_instpath=lm32_wrpc_memory
/opt/Xilinx/Vivado/2019.2/bin/updatemem -meminfo ./${proj_name}.mmi -data ${lm32_wrpc_elf} -bit ./work/${proj_name}.runs/impl_1/${proj_name}.bit -proc ${lm32_wrpc_instpath} -out ./work/${proj_name}.runs/impl_1/${proj_name}_elf.bit -force
hdl/spec7_ref_design/syn/proj_file_list.txt
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hdl/spec7_ref_design/syn/proj_properties.tcl
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#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set lm32_wrpc_initf [pwd]/../../../sw/precompiled/wrps-sw_spec7/wrc.bram
set lm32_wrpc_elf [pwd]/../../../sw/precompiled/wrps-sw_spec7/wrc.elf
set lm32_wrpc_instpath "lm32_wrpc_memory"
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_dpram_initf=$lm32_wrpc_initf"
}
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================
# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
# Reference Design (using fmc-dio-5chttla => https://ohwr.org/project/fmc-dio-5chttla/wikis/home)
# HPSEC Design (using Bulls-Eye connector)
set spec7_design spec7_ref_top
#set spec7_design spec7_hpsec_top
# ====================================================
# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================
# ====================================================
# SELECT PPS SINLGE / DIFFERENTIAL:
# ====================================================
# When Bulls-Eye connector is used as input (HPSEC).
# Differential: B01/B02 (LVDS)
# Single-ended: B11 (TTL, 5V tolerant)
set pps_in "single"
#set pps_in "diff"
# ====================================================
set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set lm32_wrpc_initf [pwd]/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.bram
set lm32_wrpc_elf [pwd]/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.elf
set lm32_wrpc_instpath "lm32_wrpc_memory"
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_design=$spec7_design \
g_use_pps_in=$pps_in \
g_dpram_initf=$lm32_wrpc_initf"
}
hdl/spec7_write_design/sim/.gitignore deleted 100644 → 0
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/spec7_write.lib
/*.bram
/*.mem
/*.bak
/*.wlf
/*.vstf
/*.lnk
/*.jou
/*.log
/transcript
\ No newline at end of file
hdl/spec7_write_design/sim/VSim_Functional.tcl deleted 100644 → 0
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set Simulation TRUE
if {$Simulation} {
puts "Note: Simulation"
set g_simulation 1
} else {
puts "Note: Synthesis"
set g_simulation 0
}
source ../../../sw/scripts/VSim_Current_Revision.tcl
puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\precompiled\\wrps-sw_v4_2_KPx5\\wrc.elf"]"
set lm32_wrpc_instpath "lm32_wrpc_memory"
# !!! Note !!!: Don't forget to compile the software (elf file) for simulation (avoid printf etc. to speed up simulation time)
# !!! Note !!!: The double \\ are there since the DOS command below needs backslashes and a single backslash is seen as a switch in tcl
# Generate a "lm32_memory.mem" file from the "elf" file content
exec cmd.exe /c updatemem -meminfo spec7_write_top.smi -data $elf_file_lm32_wrpc -proc $lm32_wrpc_instpath -force
# Convert the "mem" to a "bram" (a format used by the White Rabbit "memory_loader_pkg.vhd")
do ../../../sw/scripts/mem2bram.tcl lm32_wrpc_memory 131072
# Now a fresh "lm32_wrpc_memory.bram" is in place for simulation and is loaded into xwb_dpram
# Note that -novopt causes No Optimization (some internal signals might get non-vivible by optimization)
# Note that "-L unisim" is needed to find the primitive "BSCANE2" thta is instantiated in "$LM32_Sources/platform/kintex7/jtag_tap.v "
#suppress warning Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value <> is not in bounds of NATURAL.
#suppress warning Warning: (vsim-8684) No drivers exist on out port <blabla>
#vsim -G/spec7_write_top/g_simulation=$g_simulation -G/spec7_write_top/g_dpram_initf=lm32_wrpc_memory.bram -t ps -L unisim -lib work work.spec7_write_top
# -novopt is now deprecated
#vsim -voptargs="+acc" -novopt
# Note that -novopt can cause errors like:
# "Error: (vsim-8346) .../blabla.vhd(516): VHDL component port was not found because Verilog port 'D_ACK_I' was mapped to the extended identifier '\D_ACK_I\'."
# "Error: (vsim-3935) .../blabla.vhd(177): Port 'I_CYC_O' not found in the connected module."
vsim -voptargs="+acc=lnprv" \
-G/spec7_write_top/g_simulation=$g_simulation \
-G/spec7_write_top/g_dpram_initf=lm32_wrpc_memory.bram \
-t ps -L unisim -lib work work.spec7_write_top
do wave.tcl
do test.tcl
view signals
run 100 us
#stop
#wave zoom full
#
# End
#
hdl/spec7_write_design/sim/modelsim.ini deleted 100644 → 0
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hdl/spec7_write_design/sim/spec7_write_top.smi deleted 100644 → 0
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<?xml version="1.0" encoding="UTF-8"?>
<MemInfoSimulation Version="1" Minor="1">
<Processor Endianness="Big" InstPath="lm32_wrpc_memory">
<AddressSpace Name="lm32_wrpc_memory_dpram" ECC="NONE" Begin="0" End="131071">
<BusBlock>
<BitLane MemType="lm32_wrpc_memory_dpram" MemType_DataWidth="32" MemType_AddressDepth="131071">
<DataWidth MSB="31" LSB="0"/>
<AddressRange Begin="0" End="32767"/>
<Parity ON="false" NumBits="0"/>
<MemFile Name="lm32_wrpc_memory.mem"/>
</BitLane>
</BusBlock>
</AddressSpace>
</Processor>
<Config>
<Option Name="Part" Val="xc7k160tfbg676-2"/>
</Config>
<DRC>
<Rule Name="RDADDRCHANGE" Val="false"/>
</DRC>
</MemInfoSimulation>
hdl/spec7_write_design/sim/vlog.opt deleted 100644 → 0
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+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi
hdl/spec7_write_design/syn/.gitignore deleted 100644 → 0
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/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
hdl/spec7_write_design/syn/README.TXT deleted 100644 → 0
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Synthesis and Place&Route README.TXT January 25, 2018
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_elf.cmd combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
4) do_vivado_prog.cmd download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
hdl/spec7_write_design/syn/do_vivado.cmd deleted 100644 → 0
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rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
hdl/spec7_write_design/syn/do_vivado_gen_bin_mcs.cmd deleted 100644 → 0
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rem prog.cmd PeterJ, 23-JUl-2018.
@prompt $$$s
rem ### Clean up old log files and stuff
del vivado_gen_bin_mcs.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_gen_bin_mcs.tcl -log vivado_gen_bin_mcs.log
hdl/spec7_write_design/syn/do_vivado_mmi_elf.sh deleted 100755 → 0
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#! /bin/bash
proj_name=spec7_write_top
lm32_wrpc_elf=../../../sw/precompiled/wrps-sw_spec7/wrc.elf
lm32_wrpc_instpath=lm32_wrpc_memory
/opt/Xilinx/Vivado/2019.2/bin/updatemem -meminfo ./${proj_name}.mmi -data ${lm32_wrpc_elf} -bit ./work/${proj_name}.runs/impl_1/${proj_name}.bit -proc ${lm32_wrpc_instpath} -out ./work/${proj_name}.runs/impl_1/${proj_name}_elf.bit -force
hdl/spec7_write_design/syn/do_vivado_prog.cmd deleted 100644 → 0
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rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
hdl/spec7_write_design/syn/do_vivado_tcl.cmd deleted 100644 → 0
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rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
hdl/spec7_write_design/syn/proj_file_list.txt deleted 100644 → 0
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hdl/spec7_write_design/syn/proj_properties.tcl deleted 100644 → 0
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#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
set proj_name spec7_write_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set lm32_wrpc_initf [pwd]/../../../sw/precompiled/wrps-sw_spec7/wrc.bram
set lm32_wrpc_elf [pwd]/../../../sw/precompiled/wrps-sw_spec7/wrc.elf
set lm32_wrpc_instpath "lm32_wrpc_memory"
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_dpram_initf=$lm32_wrpc_initf"
}
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
hdl/spec7_write_design/syn/revisiondate.tcl deleted 100644 → 0
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###############################################################################
# revisiondate.tcl 08-Dec-2006
# Calculate Current Date
set current_year [clock format [clock seconds] -format %y]
scan $current_year %d current_year
set current_year_h [expr ($current_year / 10)]
set current_year_l [expr ($current_year - 10 * $current_year_h)]
set current_month [clock format [clock seconds] -format %m]
scan $current_month %d current_month
set current_month_h [expr ($current_month / 10)]
set current_month_l [expr ($current_month - 10 * $current_month_h)]
set current_day [clock format [clock seconds] -format %d]
scan $current_day %d current_day
set current_day_h [expr ($current_day / 10)]
set current_day_l [expr ($current_day - 10 * $current_day_h)]
set current_date [expr (1048576*$current_year_h + 65536*$current_year_l + 4096*$current_month_h + 256*$current_month_l + 16*$current_day_h + $current_day_l)]
# Calculate Current Revision
set revision_log_file "revisiondate_log.txt"
set current_rev_date [clock format [clock seconds] -format %y%m%d]
if [file exists $revision_log_file] {
set revision_log_fileptr [open $revision_log_file]
gets $revision_log_fileptr revision_log_date
gets $revision_log_fileptr revision_log_revnumber
close $revision_log_fileptr
if { [string compare $current_rev_date $revision_log_date] == 0 } {
# Dates are equal
set current_revision [expr ($revision_log_revnumber + 1)]
} else {
# Dates are unequal
set current_revision 0
}
set revision_log_fileptr [open $revision_log_file w]
puts $revision_log_fileptr $current_rev_date
puts $revision_log_fileptr $current_revision
close $revision_log_fileptr
} else {
puts "WARNING $revision_log_file not found. Creating new one..."
set current_revision 0
set revision_log_fileptr [open $revision_log_file w]
puts $revision_log_fileptr $current_rev_date
puts $revision_log_fileptr $current_revision
close $revision_log_fileptr
}
puts "###### Synthesis is done with the following settings:"
puts [format "###### DATE: %x" $current_date]
puts [format "###### REVISION: %d" $current_revision]
###############################################################################
wr-cores @ 6a0227ff
Subproject commit 0c446e8104a2b6f5288ec0b37655dc0f9b7d1a4c
Subproject commit 6a0227ff199ac6df6b17b3336c14eff978965538
sw/precompiled/wrps-sw-v5_spec7/.config 0 → 100644
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#
# Automatically generated file; DO NOT EDIT.
# WR PTP Core software configuration
#
# CONFIG_TARGET_GENERIC_PHY_8BIT is not set
# CONFIG_TARGET_GENERIC_PHY_16BIT is not set
# CONFIG_TARGET_WR_SWITCH is not set
# CONFIG_TARGET_AFCZ is not set
# CONFIG_TARGET_ERTM14 is not set
# CONFIG_TARGET_SIS8300KU is not set
CONFIG_TARGET_SPEC7=y
CONFIG_WR_NODE=y
CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_STACKSIZE=2048
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
CONFIG_VLAN_FOR_CLASS6=0
# CONFIG_HOST_PROCESS is not set
CONFIG_LM32=y
CONFIG_EMBEDDED_NODE=y
CONFIG_PPSI=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
# CONFIG_IPMI_CONSOLE is not set
# CONFIG_P2P is not set
# CONFIG_IP is not set
# CONFIG_CMD_CONFIG is not set
# CONFIG_BUILD_INIT is not set
CONFIG_INIT_COMMAND=""
CONFIG_HAS_BUILD_INIT=0
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
CONFIG_TRACE_MSGS=y
# CONFIG_TRACE_ALL_ENABLE is not set
# CONFIG_TRACE_MAIN_ENABLE is not set
# CONFIG_TRACE_STORAGE_ENABLE is not set
# CONFIG_TRACE_DEVICES_ENABLE is not set
CONFIG_TRACE_BOARD_ENABLE=y
# CONFIG_TRACE_MAC_ENABLE is not set
# CONFIG_TRACE_PHY_ENABLE is not set
CONFIG_TRACE_ALL=0
CONFIG_TRACE_MAIN=0
CONFIG_TRACE_STORAGE=0
CONFIG_TRACE_DEVICES=0
CONFIG_TRACE_BOARD=1
CONFIG_TRACE_MAC=0
CONFIG_TRACE_PHY=0
#
# wrpc-sw is tainted if you change the following options
#
# CONFIG_DEVELOPER is not set
CONFIG_VLAN_ARRAY_SIZE=1
CONFIG_PRINTF_XINT=y
# CONFIG_PRINTF_FULL is not set
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
sw/precompiled/wrps-sw-v5_spec7/GitLog.txt 0 → 100644
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wrpc-sw.git: b216159 (HEAD -> peter_spec7_wrpc-v5, origin/peter_spec7_wrpc-v5)
ppsi.git: bcb5817 (HEAD, origin/peter_direct_dmtd_v5, peter_direct_dmtd_v5)
for HPSEC grand-maste mode change line 43/44 of boards/spec7/board.cw into:
#define CONFIG_HPSEC_GM
//#undef CONFIG_HPSEC_GM
sw/precompiled/wrps-sw-v5_spec7/wrc.bram 0 → 100644
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sw/precompiled/wrps-sw-v5_spec7/wrc.mif 0 → 100644
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sw/precompiled/wrps-sw-v5_spec7/wrc_hpsec.bram 0 → 100644
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sw/precompiled/wrps-sw-v5_spec7/wrc_hpsec.mif 0 → 100644
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sw/scripts/do_vivado_mmi_elf.cmd
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rem prog.cmd PeterJ, 02-Jul-2020.
@prompt $$$s
set proj_name=%~n1%
set lm32_wrpc_mmi=%proj_name%.mmi
set lm32_wrpc_elf=%2%
set lm32_wrpc_instpath="lm32_wrpc_memory"
if not exist "%1%" (
@echo ### %1% ### bit file not found
@echo Usage: do_vivado_mmi_elf <bitfile>.bit <elffile>.elf
......@@ -23,15 +28,15 @@ if not "%~x2%"==".elf" (
exit /B
)
if not exist "%lm32_wrpc_mmi%" (
@echo ### %lm32_wrpc_mmi% ### mmi file not found, has it been generated?"
exit /B
)
rem ### Cleanup old log files and stuff
del vivado_mmi_elf.log
del updatemem*.jou
del updatemem*.log
set proj_name=%~n1%
set lm32_wrpc_elf=%2%
set lm32_wrpc_instpath="lm32_wrpc_memory"
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
%VIVADO%updatemem -meminfo %proj_name%.mmi -data %lm32_wrpc_elf% -bit %proj_name%.bit -proc %lm32_wrpc_instpath% -out %proj_name%_elf.bit -force >> vivado_mmi_elf.log
......
sw/scripts/do_vivado_mmi_elf.sh 0 → 100755
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#! /bin/bash
# do_vivado_mmi_elf.sh PascalB, 09-Jul-2020.
proj_name=$(basename $1 .bit)
lm32_wrpc_mmi=${proj_name}.mmi
lm32_wrpc_elf=$2
lm32_wrpc_instpath="lm32_wrpc_memory"
if not [ -f "$1" ]; then
echo "$1 bit file not found"
echo "Usage: do_vivado_mmi_elf.sh <bitfile>.bit <elffile>.elf"
exit
fi
if not [ ${1: -4} == ".bit" ]; then
echo "$1 bit file not found"
echo "Usage: do_vivado_mmi_elf.sh <bitfile>.bit <elffile>.elf"
exit
fi
if not [ -f "$2" ]; then
echo "$1 elf file not found"
echo "Usage: do_vivado_mmi_elf.sh <bitfile>.bit <elffile>.elf"
exit
fi
if not [ ${2: -4} == ".elf" ]; then
echo "$2 elf file not found"
echo "Usage: do_vivado_mmi_elf.sh <bitfile>.bit <elffile>.elf"
exit
fi
if not [ -f "$lm32_wrpc_mmi" ]; then
echo "$1 mmi file not found, has it been generated?"
exit
fi
# Cleanup old log files and stuff
rm vivado_mmi_elf.log 2>/dev/null
rm updatemem*.jou 2>/dev/null
rm updatemem*.log 2>/dev/null
updatemem -meminfo ${proj_name}.mmi -data $2 -bit $1 -proc $lm32_wrpc_instpath -out ${proj_name}_elf.bit -force >> vivado_mmi_elf.log
sw/scripts/viv_do_all.tcl
View file @ 93fd5218
......@@ -30,6 +30,7 @@ create_project -force -part $device $proj_name ./$proj_dir
# work_directory is *full* path project directory.
# Vivado doesn't seem to accept relative paths!?
set work_directory [get_property DIRECTORY [current_project]]
set_property default_lib work [current_project]
# Create a hdl_version.xdc file to set the bitfile USERID to the revision date/version
set revision_log_file "revisiondate_log.txt"
......@@ -91,13 +92,10 @@ foreach line $content {
# Read constraints file if any
# puts "xdc"
read_xdc -verbose $line
} elseif {[string range $line $line_length-4 $line_length] == ".tcl"} {
source $line
# making wrapper, using variable $design_name provided in xilinx TCL scripts.
make_wrapper -files [get_files ./$proj_dir/$proj_name.srcs/sources_1/bd/$design_name/$design_name.bd] -top
add_files -norecurse ./$proj_dir/$proj_name.srcs/sources_1/bd/$design_name/hdl/${design_name}_wrapper.vhd
set_property library work [get_files ./$proj_dir/$proj_name.srcs/sources_1/bd/$design_name/hdl/${design_name}_wrapper.vhd]
close_bd_design [get_bd_designs $design_name]
} elseif {[string range $line $line_length-3 $line_length] == ".bd"} {
# puts "xilinx bd"
read_bd $line
make_wrapper -files [get_files $line] -top -import
} elseif {[string range $line $line_length-4 $line_length] == ".bmm"} {
# Set pointer to bmm file if any
# puts "bmm"
......@@ -108,6 +106,16 @@ foreach line $content {
}
}
if {[info exists spec7_design]} {
if {$spec7_design == "spec7_ref_top"} {
puts "use spec7_wr_ref_top.xdc"
read_xdc -verbose ../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.xdc
} elseif {$spec7_design == "spec7_hpsec_top"} {
puts "use spec7_wr_hpsec_top.xdc"
read_xdc -verbose ../../wr-cores/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
}
}
# Set Top level
set_property top $proj_name [current_fileset]
set_property source_mgmt_mode All [current_project]
......@@ -129,7 +137,7 @@ close_design
# Generate a new name for .bit and .mmi file and copy to project directory.
# Create a senible name including date and time
set bitfile_name ${proj_name}_[string range $device 3 6]_[clock format [clock seconds] -format %y%m%d_%H%M]
set bitfile_name ${spec7_design}_[string range $device 3 6]_[clock format [clock seconds] -format %y%m%d_%H%M]
file copy ./work/${proj_name}.runs/impl_1/${proj_name}.bit ../${bitfile_name}.bit
file copy ./${proj_name}.mmi ../${bitfile_name}.mmi
......@@ -141,6 +149,10 @@ cd ip_cores/general-cores/ ; set general_cores_sha [exec git rev-parse HEAD]
cd $syn_dir
# write SHA codes in log a file
set git_log_fp [open ../${bitfile_name}.log w]
puts $git_log_fp "Build with following project properties:"
puts $git_log_fp "spec7_design = $spec7_design"
puts $git_log_fp "device = $device"
puts $git_log_fp "pps_in = $pps_in"
puts $git_log_fp "Build was based on the following SHA codes:"
puts $git_log_fp "spec7.git $spec7_sha"
puts $git_log_fp "wr-cores.git $wr_cores_sha"
......
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