Skip to content

S
SPEC7
Commit 7a5412b6 authored by Peter Jansweijer's avatar Peter Jansweijer
Browse files
Options

initial commit

parents
Hide whitespace changes
Inline Side-by-side
Showing with 442 additions and 0 deletions
.gitmodules 0 → 100644
View file @ 7a5412b6
[submodule "hdl/wr-cores"]
path = hdl/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
wr-cores @ 4589bf4f
Subproject commit 4589bf4f519f35c7fa5d8fd656bb5f57b2bd185f
sw/scripts/conv_file_list_to_xilinx.py 0 → 100644
View file @ 7a5412b6
#!/usr/bin/python
"""
conv_file_list_to_xilinx.py:
Converts the file that lists al files needed in the project to Xilinx ".prj" and
".ise" files. The input file list is usually a concatenation of the file list that
is generated using: "hdlmake list-files > hdlmake_list" together with a list
of CLB project files.
-------------------------------------------------------------------------------
Copyright (C) 2017 Peter Jansweijer
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>
-------------------------------------------------------------------------------
Usage:
conv_file_list_to_xilinx.py
conv_file_list_to_xilinx.py -h | --help
<name> name of the file that lists al files needed in the project.
This is usually a concatenation of the file list that is generated
using: "hdlmake list-files > hdlmake_list" together with a list
of CLB project files.
-o <name> optional design name, default: "fpga".
outputs Xilinx files <name>.prj and <name>.ise
Options:
-h --help Show this screen.
"""
import os
import sys
import datetime
import pdb
############################################################################
def prj_add_verilog(prj_file, line):
prj_file.write("verilog work " + line + "\"\n")
return()
def ise_add_verilog(ise_file, line):
ise_file.write(" <file xil_pn:name=" + line + "\" xil_pn:type=\"FILE_VERILOG\">\n")
ise_file.write(" <association xil_pn:name=\"BehavioralSimulation\"/>\n")
ise_file.write(" <association xil_pn:name=\"Implementation\"/>\n")
ise_file.write(" </file>\n")
return()
def prj_add_vhdl(prj_file, line):
prj_file.write("vhdl work " + line + "\"\n")
return()
def ise_add_vhdl(ise_file, line):
ise_file.write(" <file xil_pn:name=" + line + "\" xil_pn:type=\"FILE_VHDL\">\n")
ise_file.write(" <association xil_pn:name=\"BehavioralSimulation\"/>\n")
ise_file.write(" <association xil_pn:name=\"Implementation\"/>\n")
ise_file.write(" </file>\n")
return()
############################################################################
#
# If run from command line, we can test the library
#
"""
Usage:
conv_file_list_to_xilinx.py
conv_file_list_to_xilinx.py -h | --help
<name> name of the file that lists al files needed in the project.
This is usually a concatenation of the file list that is generated
using: "hdlmake list-files > hdlmake_list" together with a list
of CLB project files.
-o <name> optional design name, default: "fpga".
outputs Xilinx files <name>.prj and <name>.ise
Options:
-h --help Show this screen.
"""
if __name__ == "__main__":
import argparse
parser = argparse.ArgumentParser()
parser.add_argument("name", help="file list, output by: hdlmake list-files")
parser.add_argument("-oname", default="do_input_file_list.cmd", help="outfut file name ")
args = parser.parse_args()
name = args.name
oname = args.oname
if os.path.isfile(name) == True:
file_lst = open(name,"r")
if os.path.isfile(oname+".prj") == True:
os.remove(oname+".prj")
if os.path.isfile(oname+".ise") == True:
os.remove(oname+".ise")
xlx_prj_file = open(oname+".prj","w")
xlx_ise_file = open(oname+".ise","w")
timestamp = datetime.datetime.now() #micro seconds timing
for line in file_lst:
line = line.strip()
if line == "" or line[0] == "#":
pass
# for .v or .vhd file outputs add a "../" to be able to operate from a "work" subdirectory
elif line[-2:] == ".v":
prj_add_verilog(xlx_prj_file, "\"../" + line)
ise_add_verilog(xlx_ise_file, "\"../" + line)
elif line[-4:] == ".vhd":
prj_add_vhdl(xlx_prj_file, "\"../" + line)
ise_add_vhdl(xlx_ise_file, "\"../" + line)
file_lst.close()
#xlx_ise_file.write(" <file xil_pn:name=\"../../wr-cores/top/clbv2_ref_design/clbv2_wr_ref_top.ucf\" xil_pn:type=\"FILE_UCF\">\n")
#xlx_ise_file.write(" <association xil_pn:name=\"Implementation\"/>\n")
#xlx_ise_file.write(" </file>\n")
#xlx_ise_file.write(" <property xil_pn:name=\"Generics, Parameters\" xil_pn:value=\"g_dpram_initf=../../../wr-cores/bin/wrpc/wrc_phy16.bram\" xil_pn:valueState=\"non-default\"/>\n")
#xlx_ise_file.write(" <property xil_pn:name=\"Other Ngdbuild Command Line Options\" xil_pn:value=\"-bm fpga.bmm -sd %lst_Arch1Path%\" xil_pn:valueState=\"non-default\"/>\n")
#xlx_ise_file.write(" <property xil_pn:name=\"Other Bitgen Command Line Options\" xil_pn:value=\"-g UnconstrainedPins:Allow\" xil_pn:valueState=\"non-default\"/>\n")
xlx_prj_file.close()
xlx_ise_file.close()
else:
print(name + ": file not found")
sys.exit()
sw/scripts/revisiondate.tcl 0 → 100644
View file @ 7a5412b6
###############################################################################
# revisiondate.tcl 08-Dec-2006
# Calculate Current Date
set current_year [clock format [clock seconds] -format %y]
scan $current_year %d current_year
set current_year_h [expr ($current_year / 10)]
set current_year_l [expr ($current_year - 10 * $current_year_h)]
set current_month [clock format [clock seconds] -format %m]
scan $current_month %d current_month
set current_month_h [expr ($current_month / 10)]
set current_month_l [expr ($current_month - 10 * $current_month_h)]
set current_day [clock format [clock seconds] -format %d]
scan $current_day %d current_day
set current_day_h [expr ($current_day / 10)]
set current_day_l [expr ($current_day - 10 * $current_day_h)]
set current_date [expr (1048576*$current_year_h + 65536*$current_year_l + 4096*$current_month_h + 256*$current_month_l + 16*$current_day_h + $current_day_l)]
# Calculate Current Revision
set revision_log_file "revisiondate_log.txt"
set current_rev_date [clock format [clock seconds] -format %y%m%d]
if [file exists $revision_log_file] {
set revision_log_fileptr [open $revision_log_file]
gets $revision_log_fileptr revision_log_date
gets $revision_log_fileptr revision_log_revnumber
close $revision_log_fileptr
if { [string compare $current_rev_date $revision_log_date] == 0 } {
# Dates are equal
set current_revision [expr ($revision_log_revnumber + 1)]
} else {
# Dates are unequal
set current_revision 0
}
set revision_log_fileptr [open $revision_log_file w]
puts $revision_log_fileptr $current_rev_date
puts $revision_log_fileptr $current_revision
close $revision_log_fileptr
} else {
puts "WARNING $revision_log_file not found. Creating new one..."
set current_revision 0
set revision_log_fileptr [open $revision_log_file w]
puts $revision_log_fileptr $current_rev_date
puts $revision_log_fileptr $current_revision
close $revision_log_fileptr
}
puts "###### Synthesis is done with the following settings:"
puts [format "###### DATE: %x" $current_date]
puts [format "###### REVISION: %d" $current_revision]
###############################################################################
sw/scripts/viv_do_all.tcl 0 → 100644
View file @ 7a5412b6
# viv_do_all.tcl PeterJ, 24-Jan-2018.
#
# This script does:
# set project name
# set part name
# creates a new project
# imports the source files
# launches synthesis
# launches implementation
# generates a bitfile
# ------------------------------------
# set proj_name and proj_dir:
source proj_properties.tcl
# Format the raw time [clock seconds] to a date string
puts "[set date_string [clock format [clock seconds] -format "date: %y-%m-%d, time: %H:%M:%S"]] Implementation Started of $proj_name"
#Close currently open project and create a new one. (OVERWRITES PROJECT!!)
close_project -quiet
# Remove old and Create the new build directory
file delete -force $proj_dir
#file mkdir $proj_dir
create_project -force -part $device $proj_name ./$proj_dir
# work_directory is *full* path project directory.
# Vivado doesn't seem to accept relative paths!?
set work_directory [get_property DIRECTORY [current_project]]
# Create a hdl_version.xdc file to set the bitfile USERID to the revision date/version
set revision_log_file "revisiondate_log.txt"
if [file exists $revision_log_file] {
set revision_log_fileptr [open $revision_log_file]
gets $revision_log_fileptr revision_log_date
gets $revision_log_fileptr revision_log_revnumber
close $revision_log_fileptr
set userid [format "0x%6d%02d" $revision_log_date $revision_log_revnumber]
puts "Bitfile USERID set to $userid"
} else {
set userid 0xFFFFFFFF
puts "WARNING Bitfile USERID set to 0xFFFFFFFF"
}
set hdl_version_file [open hdl_version.xdc w]
puts $hdl_version_file "set_property BITSTREAM.CONFIG.USERID $userid \[current_design\]"
close $hdl_version_file
set_property target_language VHDL [current_project]
# ------------------------------------------------------------------------------
# Read source files
# ------------------------------------------------------------------------------
set fp [open "proj_file_list.txt" r]
set file_data [read $fp]
close $fp
set content [split $file_data "\n"]
set use_bmm false
foreach line $content {
puts $line
set line_length [ string length $line ]
if {[string range $line 0 0] == "#"} {
# puts "comment"
} elseif {[string range $line $line_length-2 $line_length] == ".v"} {
# puts "verilog"
read_verilog -library work $line
} elseif {[string range $line $line_length-4 $line_length] == ".vhd"} {
# puts "vhdl"
read_vhdl -library work $line
} elseif {[string range $line $line_length-4 $line_length] == ".xdc"} {
# Read constraints file if any
# puts "xdc"
read_xdc -verbose $line
} elseif {[string range $line $line_length-4 $line_length] == ".bmm"} {
# Set pointer to bmm file if any
# puts "bmm"
set use_bmm true
set bmm_file [pwd]/$line
set bmm_bd ${proj_name}_bd.bmm
add_files -norecurse $bmm_file
}
}
# Set Top level
set_property top $proj_name [current_fileset]
set_property source_mgmt_mode All [current_project]
update_compile_order -fileset sources_1
# Pass generics
set_property generic $generics [current_fileset]
puts "INFO: Reading Source Files Done!"
# ------------------------------------------------------------------------------
source $script_dir/viv_do_synt.tcl
source $script_dir/viv_do_impl.tcl
if {$use_bmm} {
source $script_dir/viv_generate_bd_bmm.tcl
}
file copy -force $proj_dir/$proj_name.runs/impl_1/$proj_name.bit .
\ No newline at end of file
sw/scripts/viv_do_impl.tcl 0 → 100644
View file @ 7a5412b6
#
# do_impl.tcl
# Implement the design
#
set_property strategy Performance_ExtraTimingOpt [get_runs impl_1]
puts "implement the design"
# Insert the command to launch implementation run here
launch_runs -verbose impl_1
puts "wait until implementation done"
# Insert the command to wait on impl_1 run here
wait_on_run impl_1
puts "generate bit file"
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
open_run impl_1
report_drc -file drc.log
report_utilization -file utilization.log
report_clocks -file clock.log
report_timing_summary -file timing.log
\ No newline at end of file
sw/scripts/viv_do_program.tcl 0 → 100644
View file @ 7a5412b6
#
# do_program.tcl
# Configure the fpga with bit file
#
# set proj_name and proj_dir (without updating the revision!):
set argv [list no_update_revision ]
set argc 2
source proj_properties.tcl
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE ${proj_name}_elf.bit [lindex [get_hw_devices] 0]
puts "Use file: ${proj_name}_elf.bit"
current_hw_device [lindex [get_hw_devices] 0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]
set_property PROBES.FILE {} [lindex [get_hw_devices] 0]
program_hw_devices [lindex [get_hw_devices] 0]
refresh_hw_device [lindex [get_hw_devices] 0]
disconnect_hw_server
sw/scripts/viv_do_synt.tcl 0 → 100644
View file @ 7a5412b6
#
# do_synt.tcl
# Synthesize the design
#
puts "synthesizing the design"
# Insert the command to launch synthesis run here
launch_runs -verbose synth_1
puts "wait until synthesis done"
# Insert the command to wait on synth_1 run here
wait_on_run synth_1
sw/scripts/viv_find_brams.tcl 0 → 100644
View file @ 7a5412b6
# viv_find_brams.tcl PeterJ, 24-Jan-2018.
#
# This script does reports all BRAMs used in the design.
# It is intended to easily find the BRAM names that are needed for the creation
# of a bmm file.
# ------------------------------------
set my_rams [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* }]
foreach ram_block $my_rams {
puts $ram_block
#report_property -all [get_cells $ram_block]
}
\ No newline at end of file
sw/scripts/viv_gen_bin_mcs.tcl 0 → 100644
View file @ 7a5412b6
#
# viv_gen_bin_mcs.tcl
# Implement the design
#
# set proj_name and proj_dir (without updating the revision!):
set argv [list no_update_revision ]
set argc 2
source proj_properties.tcl
puts "generate bin and mcs files"
#open_run impl_1
write_cfgmem -force -format mcs -interface spix4 -size 128 -loadbit {up 0x0 fpga_elf.bit} -file fpga_elf.mcs
write_cfgmem -force -format bin -size 512 -interface spix4 -loadbit {up 0x0 fpga_elf.bit} -file fpga_elf.bin
sw/scripts/viv_generate_bd_bmm.tcl 0 → 100644
View file @ 7a5412b6
#open_run impl_2
set project_bmm_files [get_files *.bmm]
set BB FALSE
# foreach fn $project_bmm_files {
# set temp [file rootname $fn]
# set bd_fn ${temp}_bd.bmm
set fn $bmm_file
set bd_fn $bmm_bd
puts "INFO: Creating file $bd_fn"
set fileID [open $fn r]
if [catch {open $bd_fn w} fileID_bd] {
puts "ERROR: Could not open file $bd_fn"
close $fileID
exit
}
while {[gets $fileID line] >= 0 } {
#puts "DEBUG: BB is $BB"
#puts "DEBUG: Line is $line"
if {[regexp {^[ \t]+BUS_BLOCK} $line]} {
set BB TRUE
puts $fileID_bd $line
continue
} elseif {[regexp {^[ \t]+END_BUS_BLOCK;} $line]} {
set BB FALSE
}
if { $BB eq "TRUE" } {
if {[regexp {(^[ \t]+([^\s]*).*);} $line match new_line inst] == 1} {
set BRAM_site [get_property SITE [get_cells $inst]]
set expression [regexp {_(.*)} $BRAM_site match bmm_string]
#puts "INFO: Located BRAM at site $BRAM_site"
set new_line "$new_line PLACED = ${bmm_string};"
#puts $new_line
puts $fileID_bd $new_line
} else {
#puts "ERROR: Script not expecting this input. Please contact Xilinx"
}
} else {
puts $fileID_bd $line
}
}
close $fileID_bd
close $fileID
# }
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment