copied processing_system_pcie.bd and created ps_pcie.bd with same processing…

copied processing_system_pcie.bd and created ps_pcie.bd with same processing system footprint as ps_pci_tandem.bd

copied processing_system_pcie.bd and created ps_pcie.bd with same processing…
copied processing_system_pcie.bd and created ps_pcie.bd with same processing system footprint as ps_pci_tandem.bd
5d456357 · Peter Jansweijer · 8301e5b3 · 5d456357 · 5d456357 · 5d456357
Commit 5d456357 authored Aug 19, 2021 by Peter Jansweijer
5 changed files
--- a/hdl/board/wr_spec7_pkg.vhd
+++ b/hdl/board/wr_spec7_pkg.vhd
@@ -154,7 +154,7 @@ package wr_spec7_pkg is
      link_ok_o            : out std_logic);
  end component xwrc_board_spec7;

-  component processing_system_pcie_wrapper is
+  component ps_pcie_wrapper is
  port (
    aclk1_0 : in STD_LOGIC;
    pcie_clk : in STD_LOGIC;
@@ -221,5 +221,5 @@ package wr_spec7_pkg is
    pcie_mgt_0_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcie_mgt_0_txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
  );
-  end component processing_system_pcie_wrapper;
+  end component ps_pcie_wrapper;
 end wr_spec7_pkg;
--- a/hdl/ip/processing_system_pcie.bd
+++ b/hdl/ip/processing_system_pcie.bd
--- a/hdl/sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
+++ b/hdl/sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
@@ -174,6 +174,6 @@ vcom -explicit -93 -work work ../../board/xwrc_board_spec7.vhd
 vcom -explicit -93 -work work ../../top/spec7_ref_design/spec7_wr_ref_top.vhd

 # Executing Vivado Block Design script:
-# ../../wr-cores/platform/xilinx/wr_pcie/Pcie.tcl
+# ../../ip/ps_pcie.bd
 # results in many file that are genearted to instantiate this functionality.
 # If a full simulation needs to be done including these Block Designs then Vivado can generate simulation files.
--- a/hdl/syn/spec7_ref_design/proj_file_list.txt
+++ b/hdl/syn/spec7_ref_design/proj_file_list.txt
@@ -175,7 +175,7 @@


 # bmm not supported by hdlmake? Need to add it manually...
-../../ip/processing_system_pcie.bd
+../../ip/ps_pcie.bd
 ../../top/spec7_ref_design/spec7_wr_ref_top.bmm

 # include hardware version ID un FPGA USER_ID register:

--- a/hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
+++ b/hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
@@ -446,7 +446,7 @@ pci_clk_buf : IBUFDS_GTE2
    CEB => '0'
  ); 

-Pcie: processing_system_pcie_wrapper
+Pcie: ps_pcie_wrapper
  port map (
    DDR_addr          =>DDR_addr         ,
    DDR_ba            =>DDR_ba           ,