Fixed an actual crucial bug, long PPS dutycycles hold statemachine

2ccb4b7a · Pascal Bos · d6cf3df7 · 2ccb4b7a
Commit 2ccb4b7a authored Oct 15, 2021 by Pascal Bos
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Showing with 20 additions and 8 deletions

wr_irigb_conv.vhd hdl/top/spec7_ref_design/wr_irigb_conv.vhd +20 -8

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--- a/hdl/top/spec7_ref_design/wr_irigb_conv.vhd
+++ b/hdl/top/spec7_ref_design/wr_irigb_conv.vhd
@@ -59,6 +59,8 @@ end wr_irigb_conv;
 architecture Behavioral of wr_irigb_conv is
  signal tai_time_s    : std_logic_vector(39 downto 0);
  signal irig_b_ctrl_s : std_logic_vector(17 downto 0);
+  signal pps_reg       : std_logic;
+  signal pps_trigger   : std_logic;
  type state_type_irig is (IDLE, PR,SEC,P1,MIN,P2,HOUR,P3,DAY_L,P4,DAY_H,P5,YEAR,P6,CTRL_1,P7,CTRL_2,P8,SBS_L,P9,SBS_H,P0,WAIT_FOR_PPS);
  signal prs,nxt : state_type_irig;
  
@@ -174,6 +176,16 @@ begin
    end if;
  end if;
 end process ctrl_register;
+
+pps_register : process (clk_i, rst_n_i ) is
+begin
+  if rst_n_i = '0' then
+    pps_reg <= '0';
+  elsif rising_edge(clk_i) then
+    pps_reg <= pps_i;
+  end if;
+end process pps_register;
+pps_trigger <= '1' when pps_i = '1' and pps_reg = '0' else '0';
 --
 -- this statement generates the 5 dividers for: Seconds&Minutes, Hours, Days, Years and SBS --
 -- it utilizes both the dividers "Answer/Quotient" and "Remainder", as can be seen below    --
@@ -264,10 +276,10 @@ irig_bit_comp <= '1' when irig_cnt = bit_time-1 else '0';
 --the driver of the irig_b outbut signal
 --this is combinatoric to ensure a same-clock cycle start with the pps.
 irig_b_o <= pps_i when (prs = IDLE or prs = WAIT_FOR_PPS) 
-            else ('0' or pps_i) when (rst_n_i = '0')               
-                                  or (irig_cnt > mark_time) 
-                                  or (irig_cnt > one_time and irig_sig = ONE)
-                                  or (irig_cnt > zero_time and irig_sig = ZERO)        
+            else '0' when (rst_n_i = '0')               
+                       or (irig_cnt > mark_time) 
+                       or (irig_cnt > one_time and irig_sig = ONE)
+                       or (irig_cnt > zero_time and irig_sig = ZERO)        
            else '1';
         
 --counts its position within the current irig_b word ( f.e.: 1,2,4,8,10,20,40)    
@@ -295,16 +307,16 @@ begin
  end if;
 end process state_register;

-next_state_decoder : process(prs,rst_n_i,pps_i,irig_word_cnt,irig_bit_comp,irig_cnt) is 
+next_state_decoder : process(prs,rst_n_i,pps_trigger,irig_word_cnt,irig_bit_comp,irig_cnt) is 
 begin
  if rst_n_i = '0' then
    nxt <= IDLE;
-  elsif pps_i = '1' then --A PPS signal will ALWAYS result in a new frame being send.
+  elsif pps_trigger = '1' then --A PPS signal will ALWAYS result in a new frame being send.
    nxt <= PR;
  else
    case prs is
    when IDLE =>  
-      nxt <= IDLE; -- stay here until pps_i jumps to PR.
+      nxt <= IDLE; -- stay here until pps_trigger jumps to PR.
    when PR =>
      if irig_bit_comp = '1' then
        nxt <= SEC;
@@ -432,7 +444,7 @@ begin
        nxt <= P0;
      end if;
    when WAIT_FOR_PPS =>
-        nxt <= WAIT_FOR_PPS; -- stay here until pps_i jumps to PR.
+        nxt <= WAIT_FOR_PPS; -- stay here until pps_trigger jumps to PR.
    end case;
  end if;
 end process next_state_decoder;