Merge remote-tracking branch 'origin/proposed_master' into develop

hdl/rtl/spec_template_wr.vhd

@@ -80,11 +80,11 @@ entity spec_template_wr is
     clk_125m_pllref_n_i : in std_logic;
 
     -- 20MHz VCXO clock (for WR)
-    clk_20m_vcxo_i : in std_logic;
+    clk_20m_vcxo_i : in std_logic  := '0';
 
     -- 125 MHz GTP reference
-    clk_125m_gtp_n_i : in std_logic;
-    clk_125m_gtp_p_i : in std_logic;
+    clk_125m_gtp_n_i : in std_logic := '0';
+    clk_125m_gtp_p_i : in std_logic := '0';
 
     ---------------------------------------------------------------------------
     -- GN4124 PCIe bridge signals
@@ -158,13 +158,13 @@ entity spec_template_wr is
     -- Green LED next to the SFP: indicates if the link is up.
     led_link_o  : out std_logic;
 
-    button1_i   : in  std_logic;
+    button1_i   : in  std_logic := '1';
 
     ---------------------------------------------------------------------------
     -- UART
     ---------------------------------------------------------------------------
 
-    uart_rxd_i : in  std_logic;
+    uart_rxd_i : in  std_logic := '1';
     uart_txd_o : out std_logic;
 
     ---------------------------------------------------------------------------
@@ -182,15 +182,15 @@ entity spec_template_wr is
 
     sfp_txp_o         : out   std_logic;
     sfp_txn_o         : out   std_logic;
-    sfp_rxp_i         : in    std_logic;
-    sfp_rxn_i         : in    std_logic;
-    sfp_mod_def0_i    : in    std_logic;          -- sfp detect
+    sfp_rxp_i         : in    std_logic := '0';
+    sfp_rxn_i         : in    std_logic := '0';
+    sfp_mod_def0_i    : in    std_logic := '0';   -- sfp detect
     sfp_mod_def1_b    : inout std_logic;          -- scl
     sfp_mod_def2_b    : inout std_logic;          -- sda
     sfp_rate_select_o : out   std_logic;
-    sfp_tx_fault_i    : in    std_logic;
+    sfp_tx_fault_i    : in    std_logic := '0';
     sfp_tx_disable_o  : out   std_logic;
-    sfp_los_i         : in    std_logic;
+    sfp_los_i         : in    std_logic := '0';
 
     ------------------------------------------
     -- DDR (bank 3)
@@ -495,7 +495,7 @@ begin  -- architecture top
       master_o (0) => carrier_wb_in,
       master_o (1) => app_wb_o
     );
-  
+
   inst_devs: entity work.spec_template_regs
     port map (
       rst_n_i    => rst_sys_62m5_n,
@@ -561,7 +561,7 @@ begin  -- architecture top
 
   fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
   fmc_presence (31 downto 1) <= (others => '0');
-  
+
   --  Metadata
   p_metadata: process (clk_sys_62m5) is
   begin
@@ -739,19 +739,19 @@ begin  -- architecture top
         clk_125m_gtp_n_i    => clk_125m_gtp_n_i,
         clk_125m_gtp_p_i    => clk_125m_gtp_p_i,
         clk_10m_ext_i       => clk_ext_10m,
-  
+
         clk_sys_62m5_o      => clk_sys_62m5,
         clk_ref_125m_o      => clk_ref_125m,
         clk_pll_aux_o       => clk_pll_aux,
         rst_sys_62m5_n_o    => rst_sys_62m5_n,
         rst_ref_125m_n_o    => rst_ref_125m_n,
         rst_pll_aux_n_o     => rst_pll_aux_n,
-  
+
         plldac_sclk_o       => plldac_sclk_o,
         plldac_din_o        => plldac_din_o,
         pll25dac_cs_n_o     => pll25dac_cs_n_o,
         pll20dac_cs_n_o     => pll20dac_cs_n_o,
-  
+
         sfp_txp_o           => sfp_txp_o,
         sfp_txn_o           => sfp_txn_o,
         sfp_rxp_i           => sfp_rxp_i,
@@ -765,12 +765,12 @@ begin  -- architecture top
         sfp_tx_fault_i      => sfp_tx_fault_i,
         sfp_tx_disable_o    => sfp_tx_disable_o,
         sfp_los_i           => sfp_los_i,
-  
+
         eeprom_sda_i        => eeprom_sda_in,
         eeprom_sda_o        => eeprom_sda_out,
         eeprom_scl_i        => eeprom_scl_in,
         eeprom_scl_o        => eeprom_scl_out,
-  
+
         onewire_i           => onewire_data,
         onewire_oen_o       => onewire_oe,
         -- Uart
@@ -781,10 +781,10 @@ begin  -- architecture top
         flash_ncs_o         => spi_ncs_o,
         flash_mosi_o        => spi_mosi_o,
         flash_miso_i        => spi_miso_i,
-  
+
         wb_slave_o          => wrc_in,
         wb_slave_i          => wrc_out_sh,
-  
+
         wrf_src_o           => wrf_src_o,
         wrf_src_i           => wrf_src_i,
         wrf_snk_o           => wrf_snk_o,
@@ -803,15 +803,15 @@ begin  -- architecture top
         wrs_rx_cfg_i        => wrs_rx_cfg_i,
         wb_eth_master_o     => wb_eth_master_o,
         wb_eth_master_i     => wb_eth_master_i,
-  
+
         abscal_txts_o       => wrc_abscal_txts_out,
         abscal_rxts_o       => wrc_abscal_rxts_out,
-  
+
         tm_link_up_o        => tm_link_up_o,
         tm_time_valid_o     => tm_time_valid_o,
         tm_tai_o            => tm_tai_o,
         tm_cycles_o         => tm_cycles_o,
-  
+
         pps_p_o             => pps_p_o,
         pps_led_o           => pps_led_o,
         link_ok_o           => link_ok_o,
@@ -896,7 +896,7 @@ begin  -- architecture top
         RST      => '0',
         CLKFBIN  => pllout_clk_fb_pllref,
         CLKIN    => clk_125m_pllref);
-    
+
     cmp_clk_62m5_buf : BUFG
       port map (
         O => clk_sys_62m5,
@@ -911,7 +911,7 @@ begin  -- architecture top
       port map (
         O => clk_ddr_333m,
         I => pllout_clk_333m);
-    
+
       -- logic AND of all async reset sources (active high)
     rstlogic_arst <= (not pllout_locked) and (not gn_rst_n_i);
 
@@ -941,10 +941,10 @@ begin  -- architecture top
       port map (
         clk_i => clk_sys_62m5,
         rst_n_i => rst_gbl_n,
-    
+
         wb_i => therm_id_out,
         wb_o => therm_id_in,
-    
+
         pps_p_i => '0',
         onewire_b => onewire_b
       );

hdl/syn/golden/Manifest.py

 target = "xilinx"
 action = "synthesis"
 
-fetchto = "../../ip_cores"
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+  fetchto = "../../ip_cores"
 
 syn_device = "xc6slx45t"
 syn_grade = "-3"
@@ -10,13 +13,28 @@ syn_project = "spec_golden.xise"
 syn_tool = "ise"
 syn_top = "spec_golden"
 
+spec_template_ucf = ['onewire', 'spi']
+board = "spec"
+ctrls = ["bank3_64b_32b" ]
+
+files = [ "buildinfo_pkg.vhd" ]
+
 modules = {
   "local" : [
-      "../../top/golden",
+      "../../top/golden", "../../syn/common"
       ],
   "git" : [
       "https://ohwr.org/project/wr-cores.git",
       "https://ohwr.org/project/general-cores.git",
       "https://ohwr.org/project/gn4124-core.git",
+      "https://ohwr.org/project/ddr3-sp6-core.git",
   ],
 }
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
+
+syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"

hdl/syn/golden/syn_extra_steps.tcl

+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+xilinx::project save
+
+xilinx::project close

hdl/top/golden/Manifest.py

-files = ["spec_golden.vhd", "spec_golden.ucf"]
+files = ["spec_golden.vhd"]
 modules = {'local': ["../../rtl"]}

hdl/top/golden/spec_golden.vhd

@@ -24,6 +24,7 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
+use work.wishbone_pkg.all;
 
 entity spec_golden is
   port (
@@ -64,10 +65,15 @@ entity spec_golden is
     gn_TX_ERROR   : in std_logic;        -- Transmit Error
     gn_VC_RDY     : in std_logic_vector(1 downto 0);  -- Channel ready
 
+    -- PCB version
+    pcbrev_i : in std_logic_vector(3 downto 0);
+
     -- Font panel LEDs
 --  LED_RED   : out std_logic;
 --  LED_GREEN : out std_logic;
 
+    button1_i   : in  std_logic;
+
     -- I2C to the FMC
     fmc0_scl_b : inout std_logic;
     fmc0_sda_b : inout std_logic;
@@ -76,11 +82,8 @@ entity spec_golden is
     fmc0_prsnt_m2c_n_i: in std_logic;
 
     onewire_b : inout std_logic;
-  
---  button1_i : in std_logic;
---  button2_i : in std_logic;
 
-    spi_sclk_o : out std_logic; 
+    spi_sclk_o : out std_logic;
     spi_ncs_o  : out std_logic;
     spi_mosi_o : out std_logic;
     spi_miso_i : in  std_logic
@@ -88,38 +91,46 @@ entity spec_golden is
 end spec_golden;
 
 architecture rtl of spec_golden is
+  signal clk_sys_62m5  : std_logic;
+  signal rst_sys_62m5_n  : std_logic;
+
+  signal gn_wb_out         : t_wishbone_master_out;
+  signal gn_wb_in          : t_wishbone_master_in;
 begin
-  inst_template: entity work.spec_template
+  inst_template: entity work.spec_template_wr
     generic map (
-      g_with_vic => true,
-      g_with_onewire => true,
-      g_with_spi => true
+      g_WITH_VIC     => True,
+      g_WITH_ONEWIRE => True,
+      g_WITH_SPI     => True,
+      g_WITH_DDR     => False,
+      g_WITH_WR      => False,
+      g_simulation   => 0
     )
     port map (
       clk_125m_pllref_p_i => clk_125m_pllref_p_i,
       clk_125m_pllref_n_i => clk_125m_pllref_n_i,
-      gn_rst_n => gn_rst_n,
-      gn_gpio => gn_gpio,
-      gn_p2l_rdy => gn_p2l_rdy,
-      gn_p2l_clk_n => gn_p2l_clk_n,
-      gn_p2l_clk_p => gn_p2l_clk_p,
-      gn_p2l_data => gn_p2l_data,
-      gn_p2l_dframe => gn_p2l_dframe,
-      gn_p2l_valid => gn_p2l_valid,
-      gn_p_wr_req => gn_p_wr_req,
-      gn_p_wr_rdy => gn_p_wr_rdy,
-      gn_rx_error => gn_rx_error,
-      gn_l2p_data => gn_l2p_data,
-      gn_l2p_dframe => gn_l2p_dframe,
-      gn_l2p_valid => gn_l2p_valid,
-      gn_l2p_clk_n => gn_l2p_clk_n,
-      gn_l2p_clk_p => gn_l2p_clk_p,
-      gn_l2p_edb => gn_l2p_edb,
-      gn_l2p_rdy => gn_l2p_rdy,
-      gn_l_wr_rdy => gn_l_wr_rdy,
-      gn_p_rd_d_rdy => gn_p_rd_d_rdy,
-      gn_tx_error => gn_tx_error,
-      gn_vc_rdy => gn_vc_rdy,
+      gn_rst_n_i => gn_rst_n,
+      gn_p2l_clk_n_i => gn_p2l_clk_n,
+      gn_p2l_clk_p_i => gn_p2l_clk_p,
+      gn_p2l_rdy_o => gn_p2l_rdy,
+      gn_p2l_dframe_i => gn_p2l_dframe,
+      gn_p2l_valid_i => gn_p2l_valid,
+      gn_p2l_data_i => gn_p2l_data,
+      gn_p_wr_req_i => gn_p_wr_req,
+      gn_p_wr_rdy_o => gn_p_wr_rdy,
+      gn_rx_error_o => gn_rx_error,
+      gn_l2p_clk_n_o => gn_l2p_clk_n,
+      gn_l2p_clk_p_o => gn_l2p_clk_p,
+      gn_l2p_dframe_o => gn_l2p_dframe,
+      gn_l2p_valid_o => gn_l2p_valid,
+      gn_l2p_edb_o => gn_l2p_edb,
+      gn_l2p_data_o => gn_l2p_data,
+      gn_l2p_rdy_i => gn_l2p_rdy,
+      gn_l_wr_rdy_i => gn_l_wr_rdy,
+      gn_p_rd_d_rdy_i => gn_p_rd_d_rdy,
+      gn_tx_error_i => gn_tx_error,
+      gn_vc_rdy_i => gn_vc_rdy,
+      gn_gpio_b => gn_gpio,
       fmc0_scl_b => fmc0_scl_b,
       fmc0_sda_b => fmc0_sda_b,
       fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
@@ -127,6 +138,25 @@ begin
       spi_sclk_o => spi_sclk_o,
       spi_ncs_o => spi_ncs_o,
       spi_mosi_o => spi_mosi_o,
-      spi_miso_i => spi_miso_i
+      spi_miso_i => spi_miso_i,
+      pcbrev_i => pcbrev_i,
+
+      ddr_dma_clk_i  => clk_sys_62m5,
+      ddr_dma_rst_n_i => rst_sys_62m5_n,
+      ddr_dma_wb_i.cyc => '0',
+      ddr_dma_wb_i.stb => '0',
+      ddr_dma_wb_i.adr => x"0000_0000",
+      ddr_dma_wb_i.sel => x"00",
+      ddr_dma_wb_i.we => '0',
+      ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
+      ddr_dma_wb_o    => open,
+
+      clk_sys_62m5_o    => clk_sys_62m5,
+      rst_sys_62m5_n_o  => rst_sys_62m5_n,
+
+      --  Everything is handled by the carrier.
+      app_wb_o         => gn_wb_out,
+      app_wb_i         => gn_wb_in
     );
+    gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
 end rtl;