3.0.4 - 2024-12-17
==================
Fixed
-----
- sw: fix crash on missing HTVIC instance during FPGA devices initialization.

3.0.3 - 2024-04-17
==================
Fixed
-----
- sw: use IRQF_ONESHOT to avoid bursts of interrupts on recent kernels

3.0.2 - 2024-03-22
==================
Fixed
-----
- sw: implement a timeout mechanism to wait for DDR Calibration

3.0.1 - 2023-10-19
==================
Changed
-------
- ci: general improvements
- bld: improved Makefiles
- hdl: automate version generation for metadata

3.0.0 - 2022-11-16
==================
Added
-----
- ci: better automation
- sw: support for Linux 5.10

Changed
-------
- sw|API change: the API to flash a bitstream moved from debugfs to sysfs to
  keep it symmetric to the SVEC driver that needed to change due to an
  incompatibility in 5.10
- hdl: update gn4124 and ddr3 ip-cores
- dist: improved RPM packaging
- bld: improved Makefiles

Fixed
-----
- sw: prevent kernel crash on invalid DMA transfer pointer
- sw: prevent objtool warning about frame pointer state mismatch
- doc: fixed building and configuration files to avoid warning on sphinx 5.x

2.1.6 - 2021-07-29
==================
Fixed
-----
- sw: improve compatibilty with newer (greater than 3.10) Linux kernel version

2.1.5 - 2021-05-18
==================
Fixed
-----
- sw: check if FPGA is programmed before loading FPGA devices
- doc: improve documentation

2.1.4 - 2020-11-23
==================
Fixed
-----
- sw: SPEC driver detects the correct FLASH only on drivers reload

2.1.3 - 2020-11-16
==================
Added
-----
- sw,drv: module parameter to ignore bitstream version check (for
development
  or debug)
  - sw: the spec-firmware-version tool can dump build-info

Fixed
-----
- hdl: DMA failures fixed with thight timing constraints

2.1.2 - 2020-11-09
==================
Fixed
-----
- sw: automatize version validation

2.1.1 - 2020-11-09
==================
Fixed
-----
- hdl: report the correct version in spec-golden design

2.1.0 - 2020-11-09
==================
Fixed
-----
- hdl: cross-page DMA failure
- sw: DMA pool memory leak
- sw: fix concurrent DMA tasklet

Changed
-------
- tst: keep the DMA interface open while testing to avoid continuos
  memory re-allocation

Added
-----
- sw: tool to firmware version inspection
- sw: FLASH partitions

2.0.2 - 2020-09-29
==================
Fixed
-----
- hdl: L2P DMA issues reported with slower hosts

2.0.0 - 2020-08-20
==================
Fixed
-----
- program 2 or more SPEC FPGAs in parallel. There is a bug in the
  GN412x chip that we fixed in software by serializing any attempt of
    parallel programming

2.0.0 - 2020-07-30
==================
Added
-----
- hdl: new testbench to test the DMA feature (read/write to DDR memory) in the
       new golden.
- sw: basic Python module to handle DMA and FPGA programming
- sw: user-space DMA interface in debugfs (read/write)
- tst: add integration tests for DMA transfers

Changed
-------
- hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers.
- hdl: Cleanup of top-levels, addition of DMA to the golden.

Fixed
-----
- hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by
       inadequate flow control.
- hdl: typo in synthesis constraints.

[1.4.15] 2020-06-03
===================
Added
----
- [hdl] ignore autogenerated files to build metadata (otherwise the repository
  is always marked as dirty)

[1.4.14] 2020-05-28
===================
Added
-----
- [hdl] export DDMTD clock output

[1.4.13]·2020-05-12
===================
Fixed
-----
-·[hdl]·report·correct·version·in·spec-base·metadata

[1.4.12] 2020-05-12
===================
Added
-----
- [hdl] metadata source-id automatic assignment

Changed
-----
- [sw] do not double remap memory

[1.4.11] 2020-05-04
===================
Added
-----
- [sw] added DMA engine channel for application to the list of resources

Changed
-----
- [sw] little code improvements