[hdl] remove obsolete test_ddr project

hdl/test_ddr/rtl/Manifest.py

-files = ["spec_ddr_test.vhd",
-         "gpio_regs.vhd"]
-
-modules = {"svn" : ["http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
-                    "http://svn.ohwr.org/gn4124-core/trunk/hdl/common/rtl",
-                    "http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl"],
-           "git" : "git://ohwr.org/hdl-core-lib/general-cores.git"}
-
-fetchto = "../ip_cores"

hdl/test_ddr/rtl/gpio_regs.vhd

----------------------------------------------------------------------------------------
--- Title          : Wishbone slave core for Control and status registers
----------------------------------------------------------------------------------------
--- File           : ../rtl/gpio_regs.vhd
--- Author         : auto-generated by wbgen2 from gpio_regs.wb
--- Created        : Thu Feb  3 17:14:27 2011
--- Standard       : VHDL'87
----------------------------------------------------------------------------------------
--- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE gpio_regs.wb
--- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
----------------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity gpio_regs is
-  port (
-    rst_n_i                                  : in     std_logic;
-    wb_clk_i                                 : in     std_logic;
-    wb_addr_i                                : in     std_logic_vector(2 downto 0);
-    wb_data_i                                : in     std_logic_vector(31 downto 0);
-    wb_data_o                                : out    std_logic_vector(31 downto 0);
-    wb_cyc_i                                 : in     std_logic;
-    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
-    wb_stb_i                                 : in     std_logic;
-    wb_we_i                                  : in     std_logic;
-    wb_ack_o                                 : out    std_logic;
--- Port for std_logic_vector field: 'Status register' in reg: 'Status'
-    gpio_stat_i                              : in     std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Control register 1' in reg: 'Control_1'
-    gpio_ctrl_1_o                            : out    std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Control register 2' in reg: 'Control_2'
-    gpio_ctrl_2_o                            : out    std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Control register 3' in reg: 'Control_3'
-    gpio_ctrl_3_o                            : out    std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Register for front panel LED control' in reg: 'LED_control'
-    gpio_led_ctrl_o                          : out    std_logic_vector(31 downto 0)
-  );
-end gpio_regs;
-
-architecture syn of gpio_regs is
-
-signal gpio_ctrl_1_int                          : std_logic_vector(31 downto 0);
-signal gpio_ctrl_2_int                          : std_logic_vector(31 downto 0);
-signal gpio_ctrl_3_int                          : std_logic_vector(31 downto 0);
-signal gpio_led_ctrl_int                        : std_logic_vector(31 downto 0);
-signal ack_sreg                                 : std_logic_vector(9 downto 0);
-signal rddata_reg                               : std_logic_vector(31 downto 0);
-signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal bwsel_reg                                : std_logic_vector(3 downto 0);
-signal rwaddr_reg                               : std_logic_vector(2 downto 0);
-signal ack_in_progress                          : std_logic      ;
-signal wr_int                                   : std_logic      ;
-signal rd_int                                   : std_logic      ;
-signal bus_clock_int                            : std_logic      ;
-signal allones                                  : std_logic_vector(31 downto 0);
-signal allzeros                                 : std_logic_vector(31 downto 0);
-
-begin
--- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-  wrdata_reg <= wb_data_i;
-  bwsel_reg <= wb_sel_i;
-  bus_clock_int <= wb_clk_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
--- 
--- Main register bank access process.
-  process (bus_clock_int, rst_n_i)
-  begin
-    if (rst_n_i = '0') then 
-      ack_sreg <= "0000000000";
-      ack_in_progress <= '0';
-      rddata_reg <= "00000000000000000000000000000000";
-      gpio_ctrl_1_int <= "00000000000000000000000000000000";
-      gpio_ctrl_2_int <= "00000000000000000000000000000000";
-      gpio_ctrl_3_int <= "00000000000000000000000000000000";
-      gpio_led_ctrl_int <= "00000000000000000000000000000000";
-    elsif rising_edge(bus_clock_int) then
--- advance the ACK generator shift register
-      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
-      ack_sreg(9) <= '0';
-      if (ack_in_progress = '1') then
-        if (ack_sreg(0) = '1') then
-          ack_in_progress <= '0';
-        else
-        end if;
-      else
-        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
-          case rwaddr_reg(2 downto 0) is
-          when "000" => 
-            if (wb_we_i = '1') then
-            else
-              rddata_reg(31 downto 0) <= gpio_stat_i;
-            end if;
-            ack_sreg(0) <= '1';
-            ack_in_progress <= '1';
-          when "001" => 
-            if (wb_we_i = '1') then
-              gpio_ctrl_1_int <= wrdata_reg(31 downto 0);
-            else
-              rddata_reg(31 downto 0) <= gpio_ctrl_1_int;
-            end if;
-            ack_sreg(0) <= '1';
-            ack_in_progress <= '1';
-          when "010" => 
-            if (wb_we_i = '1') then
-              gpio_ctrl_2_int <= wrdata_reg(31 downto 0);
-            else
-              rddata_reg(31 downto 0) <= gpio_ctrl_2_int;
-            end if;
-            ack_sreg(0) <= '1';
-            ack_in_progress <= '1';
-          when "011" => 
-            if (wb_we_i = '1') then
-              gpio_ctrl_3_int <= wrdata_reg(31 downto 0);
-            else
-              rddata_reg(31 downto 0) <= gpio_ctrl_3_int;
-            end if;
-            ack_sreg(0) <= '1';
-            ack_in_progress <= '1';
-          when "100" => 
-            if (wb_we_i = '1') then
-              gpio_led_ctrl_int <= wrdata_reg(31 downto 0);
-            else
-              rddata_reg(31 downto 0) <= gpio_led_ctrl_int;
-            end if;
-            ack_sreg(0) <= '1';
-            ack_in_progress <= '1';
-          when others =>
--- prevent the slave from hanging the bus on invalid address
-            ack_in_progress <= '1';
-            ack_sreg(0) <= '1';
-          end case;
-        end if;
-      end if;
-    end if;
-  end process;
-  
-  
--- Drive the data output bus
-  wb_data_o <= rddata_reg;
--- Status register
--- Control register 1
-  gpio_ctrl_1_o <= gpio_ctrl_1_int;
--- Control register 2
-  gpio_ctrl_2_o <= gpio_ctrl_2_int;
--- Control register 3
-  gpio_ctrl_3_o <= gpio_ctrl_3_int;
--- Register for front panel LED control
-  gpio_led_ctrl_o <= gpio_led_ctrl_int;
-  rwaddr_reg <= wb_addr_i;
--- ACK signal generation. Just pass the LSB of ACK counter.
-  wb_ack_o <= ack_sreg(0);
-end syn;

hdl/test_ddr/syn/Manifest.py

-target = "xilinx"
-action = "synthesis"
-
-syn_device = "xc6slx45t"
-syn_grade = "-3"
-syn_package = "fgg484"
-syn_top = "spec_ddr_test"
-syn_project = "spec_ddr_test.xise"
-
-files = ["../spec_ddr_test.ucf"]
-
-modules = { "local" : "../rtl" }

hdl/test_ddr/wb_gen/gpio_regs.wb

-peripheral {
-  name = "Control and status registers";
-  description = "Wishbone slave to test CSR wishbone on SPEC board";
-  hdl_entity = "gpio_regs";
-
-  prefix = "gpio";
-
-  reg {
-    name = "Status";
-    prefix = "stat";
-    field {
-      name = "Status register";
-      type = SLV;
-      size = 32;
-      access_bus = READ_ONLY;
-      access_dev = WRITE_ONLY;
-    };
-  };
-
-  reg {
-    name = "Control_1";
-    prefix = "ctrl_1";
-    field {
-      name = "Control register 1";
-      type = SLV;
-      size = 32;
-      access_bus = READ_WRITE;
-      access_dev = READ_ONLY;
-    };
-  };
-
-  reg {
-    name = "Control_2";
-    prefix = "ctrl_2";
-    field {
-      name = "Control register 2";
-      type = SLV;
-      size = 32;
-      access_bus = READ_WRITE;
-      access_dev = READ_ONLY;
-    };
-  };
-
-  reg {
-    name = "Control_3";
-    prefix = "ctrl_3";
-    field {
-      name = "Control register 3";
-      type = SLV;
-      size = 32;
-      access_bus = READ_WRITE;
-      access_dev = READ_ONLY;
-    };
-  };
-
-  reg {
-    name = "LED_control";
-    prefix = "led_ctrl";
-    field {
-      name = "Register for front panel LED control";
-      type = SLV;
-      size = 32;
-      access_bus = READ_WRITE;
-      access_dev = READ_ONLY;
-    };
-  };
-
-};