Commit cbc84788 authored by Marek Gumiński's avatar Marek Gumiński

spec_masterfip_pts2.vhd is working

parent e1f89d31
This diff is collapsed.
peripheral {
name = "FMC masterFIP PTS registers";
description = "Wishbone slave for FMC masterFIP PTS";
hdl_entity = "masterfip_pts_csr";
prefix = "mfpts";
--------------------------------------------------------------------------------------------------
reg {
name = "rst";
prefix = "rst";
description = "software reset of the masterFIP core";
field {
name = "reset of the masterFIP core";
description = "write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;\
note: there is no need to clear the bit before writing another '1'";
type = MONOSTABLE;
prefix = "core";
};
};
-------------------------------------------------------------------------------
-- external synch --
-------------------------------------------------------------------------------
reg {
name = "ext sync";
prefix = "ext_sync";
field {
name = "termination enable";
prefix = "term_en";
description = "write 0: disable 50ohms termination of the external sync pulse\
write 1: enable 50ohms termination of the external sync pulse";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "transceiver direction";
prefix = "dir";
description = "write 0: normal operation (input)\
write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "transceiver output enable";
prefix = "oe";
description = " This line is negated in the GW in order to correctly control the relay\
write 1: the external sync pulse arrives to the FPGA\
write 0: the external sync pulse does not arrive to the FPGA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External sync output value (when buffer is switched)";
prefix = "output_value";
description = "Value outputted then sync is set to output direction";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "pulses counter reset";
prefix = "p_cnt_rst";
description = "resets the pulses counter";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "FPGA IO direction";
prefix = "fpga_io_dir";
description = "Direction of FPGA IO";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "ext sync raw input";
prefix = "ext_sync_raw_input";
field {
name = "ext_sync_raw_input";
description = "External sync input value. Only valid whrn direction is set to input";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "PTS options";
prefix = "tx_corrupt";
field {
name = "enable";
description = "When corrupt is set to 1 serial tx data is forced to 0.";
prefix = "enable";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- fieldrive status signals --
-------------------------------------------------------------------------------
reg {
name = "fieldrive status";
prefix = "fd";
field {
name = "fd watchdog";
description = "fd_wdgn input from the fieldrive chip";
prefix = "wdgn";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "fd watchdog latched";
description = "Active watchdog state is latched. Register is reseted by reset core and reset fd";
prefix = "wdgn_latch";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "fd carrier detect";
description = "CDn input from the fieldrive chip";
prefix = "cd_n";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "fd transmitter error";
description = "fd_txer input from the fieldrive chip";
prefix = "txer";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg{
name = "fieldrive tx error counter";
prefix = "fd_txerr_cnt";
field {
name = "fieldrive tx error counter";
description = "Number of TX Errors. Counter is reset by macrocycle, core reset and fd reset";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
\ No newline at end of file
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......@@ -168,6 +168,18 @@ NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = LVCMOS15;
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
......@@ -177,6 +189,12 @@ NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_scl_io" LOC = F7;
NET "fmc_sda_io" LOC = F8;
NET "fmc_scl_io" IOSTANDARD = LVCMOS25;
NET "fmc_sda_io" IOSTANDARD = LVCMOS25;
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
......
This diff is collapsed.
#----------------------------------------
# BANK 0 P2V5: Clock
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# BANK 1 P1V8: PCIe interface
#----------------------------------------
NET "l_rst_n_i" LOC = N20;
NET "l_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN_o" LOC = K22;
NET "L2P_CLKN_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP_o" LOC = K21;
NET "L2P_CLKP_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME_o" LOC = U22;
NET "L2P_DFRAME_o" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB_o" LOC = U20;
NET "L2P_EDB_o" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY_i" LOC = U19;
NET "L2P_RDY_i" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID_o" LOC = T18;
NET "L2P_VALID_o" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[0]" LOC = R20;
NET "L_WR_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[1]" LOC = T22;
NET "L_WR_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN_i" LOC = M19;
NET "P2L_CLKN_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP_i" LOC = M20;
NET "P2L_CLKP_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME_i" LOC = J22;
NET "P2L_DFRAME_i" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY_o" LOC = J16;
NET "P2L_RDY_o" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID_i" LOC = L19;
NET "P2L_VALID_i" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[0]" LOC = N16;
NET "P_RD_D_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[1]" LOC = P19;
NET "P_RD_D_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[0]" LOC = L15;
NET "P_WR_RDY_o[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[1]" LOC = K16;
NET "P_WR_RDY_o[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[0]" LOC = M22;
NET "P_WR_REQ_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[1]" LOC = M21;
NET "P_WR_REQ_i[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR_o" LOC = J17;
NET "RX_ERROR_o" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR_i" LOC = M17;
NET "TX_ERROR_i" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[0]" LOC = B21;
NET "VC_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[1]" LOC = B22;
NET "VC_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[0]" LOC = P16;
NET "L2P_DATA_o[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[1]" LOC = P21;
NET "L2P_DATA_o[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[2]" LOC = P18;
NET "L2P_DATA_o[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[3]" LOC = T20;
NET "L2P_DATA_o[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[4]" LOC = V21;
NET "L2P_DATA_o[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[5]" LOC = V19;
NET "L2P_DATA_o[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[6]" LOC = W22;
NET "L2P_DATA_o[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[7]" LOC = Y22;
NET "L2P_DATA_o[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[8]" LOC = P22;
NET "L2P_DATA_o[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[9]" LOC = R22;
NET "L2P_DATA_o[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[10]" LOC = T21;
NET "L2P_DATA_o[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[11]" LOC = T19;
NET "L2P_DATA_o[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[12]" LOC = V22;
NET "L2P_DATA_o[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[13]" LOC = V20;
NET "L2P_DATA_o[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[14]" LOC = W20;
NET "L2P_DATA_o[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[15]" LOC = Y21;
NET "L2P_DATA_o[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[0]" LOC = K20;
NET "P2L_DATA_i[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[1]" LOC = H22;
NET "P2L_DATA_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[2]" LOC = H21;
NET "P2L_DATA_i[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[3]" LOC = L17;
NET "P2L_DATA_i[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[4]" LOC = K17;
NET "P2L_DATA_i[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[5]" LOC = G22;
NET "P2L_DATA_i[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[6]" LOC = G20;
NET "P2L_DATA_i[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[7]" LOC = K18;
NET "P2L_DATA_i[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[8]" LOC = K19;
NET "P2L_DATA_i[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[9]" LOC = H20;
NET "P2L_DATA_i[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[10]" LOC = J19;
NET "P2L_DATA_i[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[11]" LOC = E22;
NET "P2L_DATA_i[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[12]" LOC = E20;
NET "P2L_DATA_i[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[13]" LOC = F22;
NET "P2L_DATA_i[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[14]" LOC = F21;
NET "P2L_DATA_i[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[15]" LOC = H19;
NET "P2L_DATA_i[15]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# BANK 0 P2V5: SPEC LEDs
#----------------------------------------
NET "GPIO_b[1]" LOC = U16;
NET "GPIO_b[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO_b[0]" LOC = AB19;
NET "GPIO_b[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED_O" LOC = D5;
NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0 P2V5: SPEC DAC
#----------------------------------------
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
NET "dac_cs_n_o[1]" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = LVCMOS15;
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
# NET "fmc_scl_io" LOC = F7;
# NET "fmc_sda_io" LOC = F8;
# NET "fmc_scl_io" IOSTANDARD = LVCMOS25;
# NET "fmc_sda_io" IOSTANDARD = LVCMOS25;
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
NET "fd_txd_o" LOC = "T14";
NET "fd_txd_o" IOSTANDARD = "LVCMOS25";
NET "fd_txck_o" LOC = "W17";
NET "fd_txck_o" IOSTANDARD = "LVCMOS25";
NET "fd_txer_i" LOC = "T11";
NET "fd_txer_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxcdn_i" LOC = "T15";
NET "fd_rxcdn_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxd_i" LOC = "U15";
NET "fd_rxd_i" IOSTANDARD = "LVCMOS25";
NET "fd_wdgn_i" LOC = "R11";
NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
NET "fd_txena_o" LOC = "R13";
NET "fd_txena_o" IOSTANDARD = "LVCMOS25";
NET "speed_b0_i" LOC = Y5;
NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = A19;
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = B20;
NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_act_n_o" LOC = W10;
NET "led_sync_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_err_n_o" LOC = Y10;
NET "led_sync_err_n_o" IOSTANDARD = "LVCMOS25";
NET "tp1_o" LOC = AA16;
NET "tp1_o" IOSTANDARD = "LVCMOS25";
NET "tp2_o" LOC = AB16;
NET "tp2_o" IOSTANDARD = "LVCMOS25";
NET "tp3_o" LOC = Y17;
NET "tp3_o" IOSTANDARD = "LVCMOS25";
NET "tp4_o" LOC = AB17;
NET "tp4_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
This diff is collapsed.
......@@ -69,20 +69,17 @@ class fmcmasterfip:
# Carrier specific components
#------------------------------------
# Carrier CSR address
# TODO: recreate
CARRIER_CSR_ADDR = 0x00001200
# Masterfip core registers
MASTERFIP_CORE_ADDR = 0x00010000
CROSSBAR_MAIN = 0x10000
#------------------------------------
# MasterFIP FMC address
# eeprom
# TODO: recreate
MASTERFIP_I2C_EEPROM = CROSSBAR_MAIN + 0x1000
# Masterfip PTS core registers
MASTERFIP_CORE_PTS = 0x00011000
# Masterfip core registers
MASTERFIP_CORE_ADDR = 0x10000
# Carrier CSR address
CARRIER_CSR_ADDR = 0x00012000
# MasterFIP FMC eeprom
MASTERFIP_I2C_EEPROM = 0x00013000
freq_options = [ 31250, 1e6, 25e5, 5e6 ]
......@@ -109,9 +106,6 @@ class fmcmasterfip:
###################################################################
# creation of interfaces to modules controlling external devices
self.fmc_onewire = ow.COpenCoresOneWire(self.carrier, self.MASTERFIP_OW_THERM, 499, 99) #for 40 MHz clock
self.fmc_ds18b20 = ds18b20.CDS18B20(self.fmc_onewire, 0)
self.fmc_sys_i2c = i2c.COpenCoresI2C(self.carrier, self.MASTERFIP_I2C_EEPROM, 199)
self.fmc_eeprom_24aa64 = eeprom_24aa64.C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR)
......@@ -123,7 +117,7 @@ class fmcmasterfip:
###################### firmware initialization ####################
###################################################################
self.verify_bitstream_type();
# self.verify_carrier_status();
self.verify_carrier_status();
self.rst_core()
time.sleep(0.5)
......@@ -143,15 +137,13 @@ class fmcmasterfip:
# Returns FMC unique ID
def get_unique_id(self):
return self.fmc_ds18b20.read_serial_number()
tmp = self.fipcore.read_regname("ds1820_id_msb") << 32;
tmp |= self.fipcore.read_regname("ds1820_id_lsb");
return tmp;
# Returns FMC temperature
def get_temp(self):
serial_number = self.fmc_ds18b20.read_serial_number()
if(serial_number == -1):
return -1
else:
return self.fmc_ds18b20.read_temp(serial_number)
return self.fipcore.read_regname("ds1820_temper");
# write to EEPROM on system i2c bus
def sys_i2c_eeprom_write(self, addr, data):
......@@ -213,19 +205,12 @@ class fmcmasterfip:
# self.send_id_dat(0x7F14)
self.fipcore.write_regname('tx_ctrl', 0 )
time.sleep(0.01)
self.fipcore.write_regname('rstn', 0xCAFE0003)
time.sleep(0.5)
self.fipcore.write_regname('rstn', 0xCAFE0000)
time.sleep(0.5)
self.fipcore.write_regname('rstn', 0xCAFE0003)
self.fipcore.write_regname('rst.core', 1)
time.sleep(1)
def rst_fd(self):
self.fipcore.write_regname('rstn', 0xCAFE0003)
time.sleep(0.5)
self.fipcore.write_regname('rstn', 0xCAFE0001)
time.sleep(0.5)
self.fipcore.write_regname('rstn', 0xCAFE0003)
self.fipcore.write_regname('rst.fd', 1)
time.sleep(1)
......@@ -241,17 +226,14 @@ class fmcmasterfip:
print self.fipcore.read_regname('speed')
return self.freq_options[ self.fipcore.read_regname('speed') ]
# Disable EXT_SYNC test pulse
def disable_ext_sync_tst(self):
self.fipcore.write_regname('ext_sync', 0)
# Send ID_DAT
def send_id_dat(self, varid):
self.fipcore.write_regname('tx_ctrl', 1)
self.fipcore.write_regname('tx_ctrl', 0)
self.fipcore.write_regname('tx_data_ctrl', 0x3)
self.fipcore.write_regname('tx_data_reg1', varid)
self.fipcore.write_regname('tx_payld_ctrl', 0x3)
self.fipcore.write_regname('tx_payld_reg1', varid)
self.fipcore.write_regname('tx_ctrl', 0x202)
......@@ -259,9 +241,9 @@ class fmcmasterfip:
def read_rp_dat(self):
rx_stat = self.fipcore.read_regname('rx_stat')
rx_data_ctrl = self.fipcore.read_regname('rx_data_ctrl')
rx_data_reg1 = self.fipcore.read_regname('rx_data_reg1')
rx_data_reg2 = self.fipcore.read_regname('rx_data_reg2')
rx_data_reg3 = self.fipcore.read_regname('rx_data_reg3')
rx_data_ctrl = self.fipcore.read_regname('rx_payld_ctrl')
rx_data_reg1 = self.fipcore.read_regname('rx_payld_reg1')
rx_data_reg2 = self.fipcore.read_regname('rx_payld_reg2')
rx_data_reg3 = self.fipcore.read_regname('rx_payld_reg3')
rx_data = rx_data_reg3 << 32*2 | rx_data_reg2 << 32*1 | rx_data_reg1 << 32*0
return [ rx_stat, rx_data_ctrl, rx_data ]
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# Register definitions for slave core: FMC masterFIP PTS registers
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# * Created : Mon Mar 20 16:55:05 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
#
addr = {
'rst' : [ 0x0, 0xffffffff, "w"],
'ext_sync' : [ 0x1, 0xffffffff, "rw"],
'ext_sync.term_en' : [ 0x1, 0x1, "rw"],
'ext_sync.dir' : [ 0x1, 0x2, "rw"],
'ext_sync.oe' : [ 0x1, 0x4, "rw"],
'ext_sync.output_value' : [ 0x1, 0x8, "rw"],
'ext_sync.p_cnt_rst' : [ 0x1, 0x100, "rw"],
'ext_sync.fpga_io_dir' : [ 0x1, 0x200, "rw"],
'ext_sync_raw_input' : [ 0x2, 0xffffffff, "r"],
'tx_corrupt' : [ 0x3, 0xffffffff, "rw"],
'fd' : [ 0x4, 0xffffffff, "r"],
'fd.wdgn' : [ 0x4, 0x1, "r"],
'fd.wdgn_latch' : [ 0x4, 0x2, "r"],
'fd.cd_n' : [ 0x4, 0x4, "r"],
'fd.txer' : [ 0x4, 0x8, "r"],
'fd_txerr_cnt' : [ 0x5, 0xffffffff, "r"],
'':[0,0]
}
void main(){
printf( "Hello word");
printf( "sdf asdkfds ")
}
......@@ -233,8 +233,8 @@ def test_txerr( dut, box, maxtries = 50 ):
dut.fipcore.write_regname('tx_ctrl', 1)
dut.fipcore.write_regname('tx_ctrl', 0)
dut.fipcore.write_regname('tx_data_ctrl', 0x3)
dut.fipcore.write_regname('tx_data_reg1', 0x7F14)
dut.fipcore.write_regname('tx_payld_ctrl', 0x3)
dut.fipcore.write_regname('tx_payld_reg1', 0x7F14)
dut.fipcore.write_regname('tx_ctrl', 0x202)
time.sleep(0.5)
......@@ -286,8 +286,8 @@ def test_wdgn( dut ):
dut.fipcore.write_regname('tx_ctrl', 1)
dut.fipcore.write_regname('tx_ctrl', 0)
dut.fipcore.write_regname('tx_data_ctrl', 0x3)
dut.fipcore.write_regname('tx_data_reg1', 0x7F14)
dut.fipcore.write_regname('tx_payld_ctrl', 0x3)
dut.fipcore.write_regname('tx_payld_reg1', 0x7F14)
dut.fipcore.write_regname('tx_ctrl', 0x202)
wait_transmission_termination(dut, 100, 2 )
......@@ -305,8 +305,8 @@ def test_wdgn( dut ):
dut.fipcore.write_regname('tx_ctrl', 1)
dut.fipcore.write_regname('tx_ctrl', 0)
dut.fipcore.write_regname('tx_data_ctrl', 0x3)
dut.fipcore.write_regname('tx_data_reg1', 0x7F14)
dut.fipcore.write_regname('tx_payld_ctrl', 0x3)
dut.fipcore.write_regname('tx_payld_reg1', 0x7F14)
dut.fipcore.write_regname('tx_ctrl', 0xFFF02)
......
......@@ -13,7 +13,7 @@ INFO = True
WARRNING = True
CRITICAL = True
FIRMWARE_PATH ='gateware/syn/spec/spec_top_fmc_masterfip.bin'
FIRMWARE_PATH ='gateware/syn/spec/spec_masterfip_pts.bin'
TOPDIRNAME ="fmcmasterfip"
test03_outputpath ='/tmp/'
......
......@@ -35,3 +35,11 @@ top=`echo "$prg" | sed 's/fmcmasterfip\/.*/fmcmasterfip/'`
"$top/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb"
"$top/scripts/wbgen2" \
-D "$top/python/regs/masterfip_pts_csr.htm" \
-P "$top/python/regs/masterfip_pts_csr.py" \
-l vhdl \
-V "$top/gateware/rtl/wbgen/masterfip_pts_csr.vhd" \
"$top/gateware/rtl/wbgen/masterfip_pts_csr.wb"