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M
MasterFIP - Testing
Commit e1f89d31 authored by Marek Gumiński's avatar Marek Gumiński
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Createt wishbone fabric in top module. 

Synthesized.
i2c, main csr and mf_pts_csr must be added
parent 4a5088eb
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Showing with 77 additions and 36 deletions
gateware/top/spec/spec_masterfip_pts.vhd
View file @ e1f89d31
......@@ -323,10 +323,58 @@ architecture rtl of spec_masterfip_pts is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant C_SLAVE_ADDR : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
constant C_SLAVE_MASK : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
constant c_NUM_WB_SLAVES : integer := 4;
constant c_WB_SLAVE_MF_CORE : integer := 0;
constant c_WB_SLAVE_MF_PTS_CSR : integer := 1;
constant c_WB_SLAVE_STATUS_CSR : integer := 2;
constant c_WB_SLAVE_FMC_I2C : integer := 3;
constant c_NUM_WB_MASTERS : integer := 3;
constant c_WB_MASTER_TURTLE0 : integer := 0;
constant c_WB_MASTER_TURTLE1 : integer := 1;
constant c_WB_MASTER_FMCPERIPH : integer := 2;
constant wbmain_addr_mf_core_c : t_wishbone_address := x"0001_0000";
constant wbmain_mask_mf_core_c : t_wishbone_address := x"ffff_f000";
constant wbmain_addr_mf_pts_c : t_wishbone_address := x"0001_1000";
constant wbmain_mask_mf_pts_c : t_wishbone_address := x"ffff_f000";
constant wbmain_addr_status_c : t_wishbone_address := x"0001_2000";
constant wbmain_mask_status_c : t_wishbone_address := x"ffff_f000";
constant wbmain_addr_fmci2c_c : t_wishbone_address := x"0001_3000";
constant wbmain_mask_fmci2c_c : t_wishbone_address := x"ffff_f000";
constant wbmain_addr_c : t_wishbone_address_array( c_NUM_WB_SLAVES-1 downto 0 ) := (
c_WB_SLAVE_MF_CORE => wbmain_addr_mf_core_c,
c_WB_SLAVE_MF_PTS_CSR => wbmain_addr_mf_pts_c,
c_WB_SLAVE_STATUS_CSR => wbmain_addr_status_c,
c_WB_SLAVE_FMC_I2C => wbmain_addr_fmci2c_c
);
constant wbmain_mask_c : t_wishbone_address_array( c_NUM_WB_SLAVES-1 downto 0 ) := (
c_WB_SLAVE_MF_CORE => wbmain_mask_mf_core_c,
c_WB_SLAVE_MF_PTS_CSR => wbmain_mask_mf_pts_c,
c_WB_SLAVE_STATUS_CSR => wbmain_mask_status_c,
c_WB_SLAVE_FMC_I2C => wbmain_mask_fmci2c_c
);
signal wbmain_slaves_ms : t_wishbone_master_out_array(0 to c_NUM_WB_SLAVES-1);
signal wbmain_slaves_sm : t_wishbone_master_in_array(0 to c_NUM_WB_SLAVES-1);
signal wbmain_masters_ms : t_wishbone_master_out_array(0 to c_NUM_WB_MASTERS-1);
signal wbmain_masters_sm : t_wishbone_master_in_array(0 to c_NUM_WB_MASTERS-1);
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
......@@ -334,10 +382,7 @@ architecture rtl of spec_masterfip_pts is
signal clk_100m_sys : std_logic;
signal rst_n_sys : std_logic;
-- Mock Turtle
signal fmc_core_wb_out : t_wishbone_master_out_array(0 to 2);
signal fmc_core_wb_in : t_wishbone_master_in_array(0 to 2);
signal fmc_wb_muxed_out : t_wishbone_master_out;
signal fmc_wb_muxed_in : t_wishbone_master_in;
-- SPEC LEDs
signal led_divider : unsigned(22 downto 0);
signal leds : std_logic_vector(31 downto 0);
......@@ -413,13 +458,13 @@ begin
-- FMC presence
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_n_i,
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o(0) => fmc_core_wb_out(0), -- access from MT CPU0 at base address 0x100000
dp_master_o(1) => fmc_core_wb_out(1),
dp_master_i(0) => fmc_core_wb_in(0), -- access from MT CPU1 at base address 0x100000
dp_master_i(1) => fmc_core_wb_in(1),
dp_master_o(0) => wbmain_masters_ms(c_WB_MASTER_TURTLE0), -- access from MT CPU0 at base address 0x100000
dp_master_o(1) => wbmain_masters_ms(c_WB_MASTER_TURTLE1),
dp_master_i(0) => wbmain_masters_sm(c_WB_MASTER_TURTLE0), -- access from MT CPU1 at base address 0x100000
dp_master_i(1) => wbmain_masters_sm(c_WB_MASTER_TURTLE1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => fmc_core_wb_out(2), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => fmc_core_wb_in(2),
fmc0_host_wb_o => wbmain_masters_ms(c_WB_MASTER_FMCPERIPH), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => wbmain_masters_sm(c_WB_MASTER_FMCPERIPH),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
......@@ -438,22 +483,18 @@ begin
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_wb_crossbar : xwb_crossbar
generic map
(g_num_masters => 3,
g_num_slaves => 1,
(g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => true,
g_address => C_SLAVE_ADDR,
g_mask => C_SLAVE_MASK)
g_address => wbmain_addr_c,
g_mask => wbmain_mask_c)
port map
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_n_sys,
slave_i(0) => fmc_core_wb_out(0),
slave_i(1) => fmc_core_wb_out(1),
slave_i(2) => fmc_core_wb_out(2),
slave_o(0) => fmc_core_wb_in(0),
slave_o(1) => fmc_core_wb_in(1),
slave_o(2) => fmc_core_wb_in(2),
master_o(0) => fmc_wb_muxed_out,
master_i(0) => fmc_wb_muxed_in);
slave_i => wbmain_masters_ms,
slave_o => wbmain_masters_sm,
master_o => wbmain_slaves_ms,
master_i => wbmain_slaves_sm);
---------------------------------------------------------------------------------------------------
......@@ -489,21 +530,21 @@ begin
-- LEDs
leds_o => leds,
-- WISHBONE interface with MT CPU0 and CPU1
wb_adr_i => fmc_wb_muxed_out.adr,
wb_dat_i => fmc_wb_muxed_out.dat,
wb_stb_i => fmc_wb_muxed_out.stb,
wb_we_i => fmc_wb_muxed_out.we,
wb_cyc_i => fmc_wb_muxed_out.cyc,
wb_sel_i => fmc_wb_muxed_out.sel,
wb_dat_o => fmc_wb_muxed_in.dat,
wb_ack_o => fmc_wb_muxed_in.ack,
wb_stall_o => fmc_wb_muxed_in.stall);
wb_adr_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).adr,
wb_dat_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).dat,
wb_stb_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).stb,
wb_we_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).we,
wb_cyc_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).cyc,
wb_sel_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).sel,
wb_dat_o => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).dat,
wb_ack_o => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).ack,
wb_stall_o => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).stall);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- unused WISHBONE signals
fmc_wb_muxed_in.err <= '0';
fmc_wb_muxed_in.rty <= '0';
fmc_wb_muxed_in.int <= '0';
wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).err <= '0';
wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).rty <= '0';
wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
led_rx_act_n_o <= leds(0); -- probe on R4
......
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