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MasterFIP - Testing
Commit cbc84788 authored by Marek Gumiński's avatar Marek Gumiński
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spec_masterfip_pts2.vhd is working

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gateware/rtl/wbgen/masterfip_pts_csr.vhd 0 → 100644
View file @ cbc84788
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP PTS registers
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- Created : Mon Mar 20 16:55:05 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity masterfip_pts_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for MONOSTABLE field: 'reset of the masterFIP core' in reg: 'rst'
mfpts_rst_core_o : out std_logic;
-- Port for BIT field: 'termination enable' in reg: 'ext sync'
mfpts_ext_sync_term_en_o : out std_logic;
-- Port for BIT field: 'transceiver direction' in reg: 'ext sync'
mfpts_ext_sync_dir_o : out std_logic;
-- Port for BIT field: 'transceiver output enable' in reg: 'ext sync'
mfpts_ext_sync_oe_o : out std_logic;
-- Port for BIT field: 'External sync output value (when buffer is switched)' in reg: 'ext sync'
mfpts_ext_sync_output_value_o : out std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync'
mfpts_ext_sync_p_cnt_rst_o : out std_logic;
-- Port for BIT field: 'FPGA IO direction' in reg: 'ext sync'
mfpts_ext_sync_fpga_io_dir_o : out std_logic;
-- Port for BIT field: 'ext_sync_raw_input' in reg: 'ext sync raw input'
mfpts_ext_sync_raw_input_i : in std_logic;
-- Port for BIT field: 'enable' in reg: 'PTS options'
mfpts_tx_corrupt_enable_o : out std_logic;
-- Port for BIT field: 'fd watchdog' in reg: 'fieldrive status'
mfpts_fd_wdgn_i : in std_logic;
-- Port for BIT field: 'fd watchdog latched' in reg: 'fieldrive status'
mfpts_fd_wdgn_latch_i : in std_logic;
-- Port for BIT field: 'fd carrier detect' in reg: 'fieldrive status'
mfpts_fd_cd_n_i : in std_logic;
-- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
mfpts_fd_txer_i : in std_logic;
-- Port for std_logic_vector field: 'fieldrive tx error counter' in reg: 'fieldrive tx error counter'
mfpts_fd_txerr_cnt_i : in std_logic_vector(31 downto 0)
);
end masterfip_pts_csr;
architecture syn of masterfip_pts_csr is
signal mfpts_rst_core_dly0 : std_logic ;
signal mfpts_rst_core_int : std_logic ;
signal mfpts_ext_sync_term_en_int : std_logic ;
signal mfpts_ext_sync_dir_int : std_logic ;
signal mfpts_ext_sync_oe_int : std_logic ;
signal mfpts_ext_sync_output_value_int : std_logic ;
signal mfpts_ext_sync_p_cnt_rst_int : std_logic ;
signal mfpts_ext_sync_fpga_io_dir_int : std_logic ;
signal mfpts_tx_corrupt_enable_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
mfpts_rst_core_int <= '0';
mfpts_ext_sync_term_en_int <= '0';
mfpts_ext_sync_dir_int <= '0';
mfpts_ext_sync_oe_int <= '0';
mfpts_ext_sync_output_value_int <= '0';
mfpts_ext_sync_p_cnt_rst_int <= '0';
mfpts_ext_sync_fpga_io_dir_int <= '0';
mfpts_tx_corrupt_enable_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
mfpts_rst_core_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
mfpts_rst_core_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
mfpts_ext_sync_term_en_int <= wrdata_reg(0);
mfpts_ext_sync_dir_int <= wrdata_reg(1);
mfpts_ext_sync_oe_int <= wrdata_reg(2);
mfpts_ext_sync_output_value_int <= wrdata_reg(3);
mfpts_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
mfpts_ext_sync_fpga_io_dir_int <= wrdata_reg(9);
end if;
rddata_reg(0) <= mfpts_ext_sync_term_en_int;
rddata_reg(1) <= mfpts_ext_sync_dir_int;
rddata_reg(2) <= mfpts_ext_sync_oe_int;
rddata_reg(3) <= mfpts_ext_sync_output_value_int;
rddata_reg(8) <= mfpts_ext_sync_p_cnt_rst_int;
rddata_reg(9) <= mfpts_ext_sync_fpga_io_dir_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mfpts_ext_sync_raw_input_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
mfpts_tx_corrupt_enable_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= mfpts_tx_corrupt_enable_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mfpts_fd_wdgn_i;
rddata_reg(1) <= mfpts_fd_wdgn_latch_i;
rddata_reg(2) <= mfpts_fd_cd_n_i;
rddata_reg(3) <= mfpts_fd_txer_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mfpts_fd_txerr_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- reset of the masterFIP core
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mfpts_rst_core_dly0 <= '0';
mfpts_rst_core_o <= '0';
elsif rising_edge(clk_sys_i) then
mfpts_rst_core_dly0 <= mfpts_rst_core_int;
mfpts_rst_core_o <= mfpts_rst_core_int and (not mfpts_rst_core_dly0);
end if;
end process;
-- termination enable
mfpts_ext_sync_term_en_o <= mfpts_ext_sync_term_en_int;
-- transceiver direction
mfpts_ext_sync_dir_o <= mfpts_ext_sync_dir_int;
-- transceiver output enable
mfpts_ext_sync_oe_o <= mfpts_ext_sync_oe_int;
-- External sync output value (when buffer is switched)
mfpts_ext_sync_output_value_o <= mfpts_ext_sync_output_value_int;
-- pulses counter reset
mfpts_ext_sync_p_cnt_rst_o <= mfpts_ext_sync_p_cnt_rst_int;
-- FPGA IO direction
mfpts_ext_sync_fpga_io_dir_o <= mfpts_ext_sync_fpga_io_dir_int;
-- ext_sync_raw_input
-- enable
mfpts_tx_corrupt_enable_o <= mfpts_tx_corrupt_enable_int;
-- fd watchdog
-- fd watchdog latched
-- fd carrier detect
-- fd transmitter error
-- fieldrive tx error counter
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
gateware/rtl/wbgen/masterfip_pts_csr.wb 0 → 100644
View file @ cbc84788
peripheral {
name = "FMC masterFIP PTS registers";
description = "Wishbone slave for FMC masterFIP PTS";
hdl_entity = "masterfip_pts_csr";
prefix = "mfpts";
--------------------------------------------------------------------------------------------------
reg {
name = "rst";
prefix = "rst";
description = "software reset of the masterFIP core";
field {
name = "reset of the masterFIP core";
description = "write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;\
note: there is no need to clear the bit before writing another '1'";
type = MONOSTABLE;
prefix = "core";
};
};
-------------------------------------------------------------------------------
-- external synch --
-------------------------------------------------------------------------------
reg {
name = "ext sync";
prefix = "ext_sync";
field {
name = "termination enable";
prefix = "term_en";
description = "write 0: disable 50ohms termination of the external sync pulse\
write 1: enable 50ohms termination of the external sync pulse";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "transceiver direction";
prefix = "dir";
description = "write 0: normal operation (input)\
write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "transceiver output enable";
prefix = "oe";
description = " This line is negated in the GW in order to correctly control the relay\
write 1: the external sync pulse arrives to the FPGA\
write 0: the external sync pulse does not arrive to the FPGA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External sync output value (when buffer is switched)";
prefix = "output_value";
description = "Value outputted then sync is set to output direction";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "pulses counter reset";
prefix = "p_cnt_rst";
description = "resets the pulses counter";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "FPGA IO direction";
prefix = "fpga_io_dir";
description = "Direction of FPGA IO";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "ext sync raw input";
prefix = "ext_sync_raw_input";
field {
name = "ext_sync_raw_input";
description = "External sync input value. Only valid whrn direction is set to input";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "PTS options";
prefix = "tx_corrupt";
field {
name = "enable";
description = "When corrupt is set to 1 serial tx data is forced to 0.";
prefix = "enable";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- fieldrive status signals --
-------------------------------------------------------------------------------
reg {
name = "fieldrive status";
prefix = "fd";
field {
name = "fd watchdog";
description = "fd_wdgn input from the fieldrive chip";
prefix = "wdgn";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "fd watchdog latched";
description = "Active watchdog state is latched. Register is reseted by reset core and reset fd";
prefix = "wdgn_latch";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "fd carrier detect";
description = "CDn input from the fieldrive chip";
prefix = "cd_n";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "fd transmitter error";
description = "fd_txer input from the fieldrive chip";
prefix = "txer";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg{
name = "fieldrive tx error counter";
prefix = "fd_txerr_cnt";
field {
name = "fieldrive tx error counter";
description = "Number of TX Errors. Counter is reset by macrocycle, core reset and fd reset";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
\ No newline at end of file
gateware/syn/spec/spec_fmc_masterfip_pts.xise
View file @ cbc84788
......@@ -133,9 +133,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_masterfip_pts|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_masterfip_pts.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_masterfip_pts" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_masterfip_mt|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../ip_cores/gw-masterfip/top/spec/spec_masterfip_mt.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_masterfip_mt" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -197,7 +197,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_masterfip_pts" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_masterfip_mt" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -211,10 +211,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_masterfip_pts_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_masterfip_pts_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_masterfip_pts_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_masterfip_pts_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_masterfip_mt_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_masterfip_mt_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_masterfip_mt_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_masterfip_mt_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -382,13 +382,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -406,13 +406,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -442,7 +442,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
......@@ -475,7 +475,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -493,7 +493,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -502,7 +502,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -523,7 +523,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -544,7 +544,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
......@@ -562,16 +562,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
......@@ -586,7 +586,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -595,7 +595,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -607,7 +607,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
......@@ -622,13 +622,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram_mixed.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -691,7 +691,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -727,7 +727,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -748,7 +748,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
......@@ -766,26 +766,26 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterfip_pts.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterfip_pts.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="278"/>
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="279"/>
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="280"/>
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="281"/>
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="285"/>
......@@ -793,7 +793,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="286"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="287"/>
......@@ -817,7 +817,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="293"/>
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="294"/>
......@@ -865,11 +865,11 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="305"/>
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="306"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="307"/>
......@@ -1133,11 +1133,11 @@
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core_with_etherbone.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="378"/>
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="379"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="380"/>
......@@ -1221,15 +1221,15 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="400"/>
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="401"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="402"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="403"/>
......@@ -1237,7 +1237,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="405"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="406"/>
......@@ -1245,11 +1245,11 @@
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="407"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="408"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="409"/>
......@@ -1263,11 +1263,11 @@
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="411"/>
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="412"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="413"/>
......@@ -1295,7 +1295,7 @@
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="419"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="420"/>
......@@ -1319,7 +1319,7 @@
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="425"/>
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="426"/>
......@@ -1355,11 +1355,11 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="451"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="453"/>
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterfip_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="454"/>
......@@ -1367,7 +1367,7 @@
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="455"/>
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="456"/>
......@@ -1375,7 +1375,7 @@
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="457"/>
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="458"/>
......@@ -1383,7 +1383,7 @@
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="459"/>
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="460"/>
......@@ -1395,19 +1395,19 @@
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="462"/>
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="463"/>
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="464"/>
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterfip_wbgen2_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="465"/>
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="466"/>
......@@ -1415,11 +1415,11 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="475"/>
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="476"/>
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="477"/>
......@@ -1491,15 +1491,15 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="495"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="496"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="497"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_status_bytes_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="498"/>
......@@ -1507,21 +1507,32 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="499"/>
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="500"/>
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_wb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="501"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/top/spec/spec_masterfip_mt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="427"/>
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/top/spec/spec_masterfip_mt.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings>
<binding xil_pn:location="/spec_top_fmc_masterfip" xil_pn:name="../../top/spec/spec_top_fmc_masterfip.ucf"/>
<binding xil_pn:location="/spec_top_fmc_masterfip" xil_pn:name="../../top/spec/spec_masterfip_pts.ucf"/>
<binding xil_pn:location="/spec_masterfip_pts" xil_pn:name="../../ip_cores/gw-masterfip/top/spec/spec_masterfip_mt.ucf"/>
</bindings>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
......
gateware/syn/spec/spec_masterfip_mt.xise 0 → 100644
View file @ cbc84788
This source diff could not be displayed because it is too large. You can view the blob instead.
gateware/top/spec/spec_masterfip_pts.ucf
View file @ cbc84788
......@@ -168,6 +168,18 @@ NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = LVCMOS15;
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
......@@ -177,6 +189,12 @@ NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_scl_io" LOC = F7;
NET "fmc_sda_io" LOC = F8;
NET "fmc_scl_io" IOSTANDARD = LVCMOS25;
NET "fmc_sda_io" IOSTANDARD = LVCMOS25;
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
......
gateware/top/spec/spec_masterfip_pts.vhd
View file @ cbc84788
......@@ -200,11 +200,18 @@ entity spec_masterfip_pts is
led_green_o : out std_logic; -- blinking with clk_100m_sys
led_red_o : out std_logic; -- active during a PCIe rst, l_rst_n_i
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- FMC signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FMC presence
fmc_prsnt_m2c_n_i : in std_logic; -- FMC presence (used by MT)
-- fmc i2c interface
fmc_scl_io : inout std_logic;
fmc_sda_io : inout std_logic;
-- FMC 1-wire
fmc_onewire_b : inout std_logic; -- temper and unique id
......@@ -321,15 +328,75 @@ architecture rtl of spec_masterfip_pts is
rmq_config => C_RMQ_CONFIG,
shared_mem_size => 65536); -- in bytes
constant c_wb_spec_csr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603",
version => x"00000001",
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_MASTERFIP_SDB_DEVICE : t_sdb_device :=(
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000FFF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000AAA", -- ...
version => x"00000001",
date => x"20151006",
name => "WB-MASTERFIP.CSR ")));
constant c_MASTERFIP_PTS_SDB_DEVICE : t_sdb_device :=(
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000AAA", -- ...
version => x"00000001",
date => x"20151006",
name => "WB-MASTERFIP.CSR ")));
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant c_SDB_ADDRESS : t_wishbone_address := x"0000_0000";
constant c_fmc_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000_ffff", x"0000_0000");
constant c_fmc_bridge_record_sdb : t_sdb_record := f_sdb_embed_bridge( c_fmc_bridge_sdb, x"0001_0000");
constant c_NUM_WB_SLAVES : integer := 4;
constant c_WB_SLAVE_MF_CORE : integer := 0;
constant c_WB_SLAVE_MF_PTS_CSR : integer := 1;
constant c_WB_SLAVE_STATUS_CSR : integer := 2;
constant c_WB_SLAVE_FMC_I2C : integer := 3;
constant c_WB_SLAVE_STATUS_CSR : integer := 0;
constant c_WB_SLAVE_FMC_I2C : integer := 1;
constant c_WB_SLAVE_MF_PTS_CSR : integer := 2;
constant c_WB_SLAVE_MF_CORE : integer := 3;
constant c_NUM_WB_MASTERS : integer := 3;
......@@ -339,33 +406,43 @@ architecture rtl of spec_masterfip_pts is
constant wbmain_addr_mf_core_c : t_wishbone_address := x"0001_0000";
constant wbmain_mask_mf_core_c : t_wishbone_address := x"ffff_f000";
-- constant wbmain_addr_mf_core_c : t_wishbone_address := x"0001_0000";
-- constant wbmain_mask_mf_core_c : t_wishbone_address := x"ffff_f000";
constant wbmain_addr_mf_pts_c : t_wishbone_address := x"0001_1000";
constant wbmain_mask_mf_pts_c : t_wishbone_address := x"ffff_f000";
-- constant wbmain_addr_mf_pts_c : t_wishbone_address := x"0001_1000";
-- constant wbmain_mask_mf_pts_c : t_wishbone_address := x"ffff_f000";
constant wbmain_addr_status_c : t_wishbone_address := x"0001_2000";
constant wbmain_mask_status_c : t_wishbone_address := x"ffff_f000";
-- constant wbmain_addr_status_c : t_wishbone_address := x"0001_2000";
-- constant wbmain_mask_status_c : t_wishbone_address := x"ffff_f000";
constant wbmain_addr_fmci2c_c : t_wishbone_address := x"0001_3000";
constant wbmain_mask_fmci2c_c : t_wishbone_address := x"ffff_f000";
-- constant wbmain_addr_fmci2c_c : t_wishbone_address := x"0001_3000";
-- constant wbmain_mask_fmci2c_c : t_wishbone_address := x"ffff_f000";
constant wbmain_addr_c : t_wishbone_address_array( c_NUM_WB_SLAVES-1 downto 0 ) := (
c_WB_SLAVE_MF_CORE => wbmain_addr_mf_core_c,
c_WB_SLAVE_MF_PTS_CSR => wbmain_addr_mf_pts_c,
c_WB_SLAVE_STATUS_CSR => wbmain_addr_status_c,
c_WB_SLAVE_FMC_I2C => wbmain_addr_fmci2c_c
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) :=
(
c_WB_SLAVE_STATUS_CSR => f_sdb_embed_device(c_wb_spec_csr_sdb, x"0000_4000"),
c_WB_SLAVE_FMC_I2C => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"0000_5000"),
c_WB_SLAVE_MF_PTS_CSR => f_sdb_embed_device(c_MASTERFIP_PTS_SDB_DEVICE, x"0000_6000"),
c_WB_SLAVE_MF_CORE => f_sdb_embed_device(c_MASTERFIP_SDB_DEVICE, x"0000_7000")
);
-- constant wbmain_addr_c : t_wishbone_address_array( c_NUM_WB_SLAVES-1 downto 0 ) := (
-- c_WB_SLAVE_MF_CORE => wbmain_addr_mf_core_c,
-- c_WB_SLAVE_MF_PTS_CSR => wbmain_addr_mf_pts_c,
-- c_WB_SLAVE_STATUS_CSR => wbmain_addr_status_c,
-- c_WB_SLAVE_FMC_I2C => wbmain_addr_fmci2c_c
);
-- );
constant wbmain_mask_c : t_wishbone_address_array( c_NUM_WB_SLAVES-1 downto 0 ) := (
c_WB_SLAVE_MF_CORE => wbmain_mask_mf_core_c,
c_WB_SLAVE_MF_PTS_CSR => wbmain_mask_mf_pts_c,
c_WB_SLAVE_STATUS_CSR => wbmain_mask_status_c,
c_WB_SLAVE_FMC_I2C => wbmain_mask_fmci2c_c
-- constant wbmain_mask_c : t_wishbone_address_array( c_NUM_WB_SLAVES-1 downto 0 ) := (
-- c_WB_SLAVE_MF_CORE => wbmain_mask_mf_core_c,
-- c_WB_SLAVE_MF_PTS_CSR => wbmain_mask_mf_pts_c,
-- c_WB_SLAVE_STATUS_CSR => wbmain_mask_status_c,
-- c_WB_SLAVE_FMC_I2C => wbmain_mask_fmci2c_c
);
-- );
......@@ -390,6 +467,14 @@ architecture rtl of spec_masterfip_pts is
signal fd_txd : std_logic;
-- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic;
signal sys_scl_oe_n : std_logic;
signal sys_sda_in : std_logic;
signal sys_sda_out : std_logic;
signal sys_sda_oe_n : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -421,7 +506,9 @@ begin
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
g_system_clock_freq => 100000000, -- both CPUs at 100 MHz
g_wr_node_config => C_NODE_CONFIG)
g_wr_node_config => C_NODE_CONFIG,
g_fmc0_sdb => c_fmc_bridge_record_sdb
)
port map
(clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
......@@ -481,13 +568,14 @@ begin
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note that in the MT firmware the CPU1 is only accessing the masterfip_leds register for debugging
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_wb_crossbar : xwb_crossbar
cmp_wb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => true,
g_address => wbmain_addr_c,
g_mask => wbmain_mask_c)
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_n_sys,
......@@ -504,7 +592,8 @@ begin
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
values_for_simul => g_simulation
)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_n_sys,
......@@ -584,6 +673,75 @@ begin
led_red_o <= not rst_n_sys;
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr : entity work.carrier_csr
port map(
rst_n_i => rst_n_sys,
clk_sys_i => clk_100m_sys,
wb_adr_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).adr(3 downto 2), -- wbmain_slaves_ms.adr is byte address
wb_dat_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).dat,
wb_dat_o => wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).dat,
wb_cyc_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).cyc,
wb_sel_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).sel,
wb_stb_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).stb,
wb_we_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).we,
wb_ack_o => wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).ack,
wb_stall_o => open,
carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE,
carrier_csr_stat_fmc_pres_i => fmc_prsnt_m2c_n_i,
carrier_csr_stat_p2l_pll_lck_i => '1',
carrier_csr_stat_sys_pll_lck_i => '1',
carrier_csr_stat_ddr3_cal_done_i => '1',
carrier_csr_ctrl_led_green_o => open,
carrier_csr_ctrl_led_red_o => open,
carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_rst_fmc0_n_o => open,
carrier_csr_rst_fmc0_n_i => '0',
carrier_csr_rst_fmc0_n_load_o => open
);
-- Mezzanine system managment I2C master
-- Access to mezzanine EEPROM
------------------------------------------------------------------------------
cmp_fmc_sys_i2c : xwb_i2c_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_100m_sys,
rst_n_i => rst_n_sys,
slave_i => wbmain_slaves_ms(c_WB_SLAVE_FMC_I2C),
slave_o => wbmain_slaves_sm(c_WB_SLAVE_FMC_I2C),
desc_o => open,
scl_pad_i(0) => sys_scl_in,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => sys_sda_in,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
fmc_scl_io <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
sys_scl_in <= fmc_scl_io;
fmc_sda_io <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
sys_sda_in <= fmc_sda_io;
-- Tri-state buffer for SDA and SCL
end rtl;
--=================================================================================================
-- architecture end
......
gateware/top/spec/spec_masterfip_pts2.ucf 0 → 100644
View file @ cbc84788
#----------------------------------------
# BANK 0 P2V5: Clock
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# BANK 1 P1V8: PCIe interface
#----------------------------------------
NET "l_rst_n_i" LOC = N20;
NET "l_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN_o" LOC = K22;
NET "L2P_CLKN_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP_o" LOC = K21;
NET "L2P_CLKP_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME_o" LOC = U22;
NET "L2P_DFRAME_o" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB_o" LOC = U20;
NET "L2P_EDB_o" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY_i" LOC = U19;
NET "L2P_RDY_i" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID_o" LOC = T18;
NET "L2P_VALID_o" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[0]" LOC = R20;
NET "L_WR_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[1]" LOC = T22;
NET "L_WR_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN_i" LOC = M19;
NET "P2L_CLKN_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP_i" LOC = M20;
NET "P2L_CLKP_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME_i" LOC = J22;
NET "P2L_DFRAME_i" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY_o" LOC = J16;
NET "P2L_RDY_o" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID_i" LOC = L19;
NET "P2L_VALID_i" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[0]" LOC = N16;
NET "P_RD_D_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[1]" LOC = P19;
NET "P_RD_D_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[0]" LOC = L15;
NET "P_WR_RDY_o[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[1]" LOC = K16;
NET "P_WR_RDY_o[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[0]" LOC = M22;
NET "P_WR_REQ_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[1]" LOC = M21;
NET "P_WR_REQ_i[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR_o" LOC = J17;
NET "RX_ERROR_o" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR_i" LOC = M17;
NET "TX_ERROR_i" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[0]" LOC = B21;
NET "VC_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[1]" LOC = B22;
NET "VC_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[0]" LOC = P16;
NET "L2P_DATA_o[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[1]" LOC = P21;
NET "L2P_DATA_o[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[2]" LOC = P18;
NET "L2P_DATA_o[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[3]" LOC = T20;
NET "L2P_DATA_o[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[4]" LOC = V21;
NET "L2P_DATA_o[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[5]" LOC = V19;
NET "L2P_DATA_o[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[6]" LOC = W22;
NET "L2P_DATA_o[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[7]" LOC = Y22;
NET "L2P_DATA_o[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[8]" LOC = P22;
NET "L2P_DATA_o[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[9]" LOC = R22;
NET "L2P_DATA_o[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[10]" LOC = T21;
NET "L2P_DATA_o[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[11]" LOC = T19;
NET "L2P_DATA_o[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[12]" LOC = V22;
NET "L2P_DATA_o[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[13]" LOC = V20;
NET "L2P_DATA_o[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[14]" LOC = W20;
NET "L2P_DATA_o[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[15]" LOC = Y21;
NET "L2P_DATA_o[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[0]" LOC = K20;
NET "P2L_DATA_i[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[1]" LOC = H22;
NET "P2L_DATA_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[2]" LOC = H21;
NET "P2L_DATA_i[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[3]" LOC = L17;
NET "P2L_DATA_i[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[4]" LOC = K17;
NET "P2L_DATA_i[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[5]" LOC = G22;
NET "P2L_DATA_i[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[6]" LOC = G20;
NET "P2L_DATA_i[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[7]" LOC = K18;
NET "P2L_DATA_i[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[8]" LOC = K19;
NET "P2L_DATA_i[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[9]" LOC = H20;
NET "P2L_DATA_i[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[10]" LOC = J19;
NET "P2L_DATA_i[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[11]" LOC = E22;
NET "P2L_DATA_i[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[12]" LOC = E20;
NET "P2L_DATA_i[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[13]" LOC = F22;
NET "P2L_DATA_i[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[14]" LOC = F21;
NET "P2L_DATA_i[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[15]" LOC = H19;
NET "P2L_DATA_i[15]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# BANK 0 P2V5: SPEC LEDs
#----------------------------------------
NET "GPIO_b[1]" LOC = U16;
NET "GPIO_b[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO_b[0]" LOC = AB19;
NET "GPIO_b[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED_O" LOC = D5;
NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0 P2V5: SPEC DAC
#----------------------------------------
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
NET "dac_cs_n_o[1]" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = LVCMOS15;
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
# NET "fmc_scl_io" LOC = F7;
# NET "fmc_sda_io" LOC = F8;
# NET "fmc_scl_io" IOSTANDARD = LVCMOS25;
# NET "fmc_sda_io" IOSTANDARD = LVCMOS25;
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
NET "fd_txd_o" LOC = "T14";
NET "fd_txd_o" IOSTANDARD = "LVCMOS25";
NET "fd_txck_o" LOC = "W17";
NET "fd_txck_o" IOSTANDARD = "LVCMOS25";
NET "fd_txer_i" LOC = "T11";
NET "fd_txer_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxcdn_i" LOC = "T15";
NET "fd_rxcdn_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxd_i" LOC = "U15";
NET "fd_rxd_i" IOSTANDARD = "LVCMOS25";
NET "fd_wdgn_i" LOC = "R11";
NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
NET "fd_txena_o" LOC = "R13";
NET "fd_txena_o" IOSTANDARD = "LVCMOS25";
NET "speed_b0_i" LOC = Y5;
NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = A19;
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = B20;
NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_act_n_o" LOC = W10;
NET "led_sync_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_err_n_o" LOC = Y10;
NET "led_sync_err_n_o" IOSTANDARD = "LVCMOS25";
NET "tp1_o" LOC = AA16;
NET "tp1_o" IOSTANDARD = "LVCMOS25";
NET "tp2_o" LOC = AB16;
NET "tp2_o" IOSTANDARD = "LVCMOS25";
NET "tp3_o" LOC = Y17;
NET "tp3_o" IOSTANDARD = "LVCMOS25";
NET "tp4_o" LOC = AB17;
NET "tp4_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
gateware/top/spec/spec_masterfip_pts2.vhd 0 → 100644
View file @ cbc84788
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_masterfip_pts2 |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_masterfip_pts2.vhd |
-- |
-- Description Top level of the masterFIP design with Mock Turtle on a SPEC carrier. |
-- |
-- Figure 1 shows the architecture and main components of the design. |
-- ______________________________________________________________________ |
-- | | |
-- | _________________________________________ | |
-- | | MOCK TURTLE | | |
-- _ | | _____ | | |
-- | | | | ___ | | | | |
-- |F| | . .| . . . . . . . . . . . >| | | | | | |
-- |I| | _____ . | | | | | | | |
-- |E| | | | . | . . . . . . . .>| | | | | | |
-- |L| <--| | | . | . HMQs | | | | | | |
-- |D| | | F | . | . | | | | | | |
-- |R| | | M | . | ______ | | | | | | |
-- |I| -->| | C | . | DP | | | | | | | | |
-- |V| | | | . .|. .>| CPU0 | _____ | X | | G | | | |
-- |E| | | M | ____ . | |______| | | | b | | N | | | <-PCIe->|
-- |_| | | A | | | . | | SH. | | a | | 4 | | | host |
-- | | S |....|Xbar|... | ______ | MEM | | r | | 1 | | | |
-- ext pulse --> | | T | |____| . | | | |_____| | | | 2 | | | |
-- | | E | . | DP | CPU1 | | | | 4 | | | |
-- | | R | . .|. .>|______| | | | | | | |
-- FMC 1wire <-->| | F | | . | | | | | | |
-- | | I | | . HMQs | | | | | | |
-- | | P | | . . . . . . . . >|___| | | | | |
-- FMC LEDs <--| | | | |_____| | | |
-- | |_____| | _^_ | | |
-- | | | | | | |
-- | | |VIC| | | |
-- | | |___| | | |
-- | |_________________________________________| | |
-- |______________________________________________________________________| |
-- Figure 1: spec_masterfip_pts2 architecture |
-- |
-- |
-- FMC MASTERFIP CORE: |
-- On one side the FMC MASTERFIP CORE is the interface to the FMC hardware (i.e. |
-- FielDrive chip, external pulse LEMO, 1-wire DS18B20 chip, LEDs) on the other side |
-- it provides a wbgen2 WISHBONE where a set of control and status registers have |
-- been defined to interface with the MOCK TURTLE. |
-- The core ignores the notion of the WorldFIP frame type (ID_DAT/RT_DAT/..etc), |
-- or the macrocycle sequence and macrocycle timing; the sw running on the Mock |
-- Turtle CPUs is responsible for managing these aspects and for providing to this |
-- core all the payload bytes (coming from the host) that have to be serializedand, |
-- together with a serialization startup trigger, or for enabling the deserializer |
-- and then providing to the host the deserialized bytes. |
-- Figure 2 shows the structure of a WorldFIP frame. The core is internally |
-- generating (in the case of serialization) or validating (in the case of |
-- deserialization) only the FSS, CRC and FES bytes; the rest of the bytes are |
-- retrieved from or provided to the MOCK TURTLE. The core also encodes/decodes all |
-- the bytes to/from the Manchester2 code (as specified by the WorldFIP protocol) and|
-- controls/monitors all the FielDrive signals. |
-- _____________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________Payload_____________|_____CRC____|__FES__| |
-- |
-- Figure 2: WorldFIP frame structure |
-- |
-- MOCK TURTLE: |
-- Instead of having a big FSM in HDL that would be executing the WorldFIP |
-- macrocycle, we have software running on an embedded CPU, in order to add |
-- flexibility and ease the implementation of the design. Mock Turtle is the |
-- generic core that offers multi-CPU processing and all the infrastructure around. |
-- The interface between the CPUs and the PCIe host is though HostMessageQueues(HMQ).|
-- The interface between the CPUs with the FMC MASTERFIP CORE is a set of wbgen2- |
-- generated registers. |
-- In this design MT is configured with 2 CPUs: |
-- - CPU0 is the heart of the design; it is "playing" the WorldFIP macrocycle. |
-- For example,it initiates the delivery of a WorldFIP question frame, by providing|
-- the frame bytes to the FMC MASTERFIP CORE, and then awaits for the reception of |
-- the response frame.It retrieves these consumed data from the FMC MASTERFIP CORE,|
-- packs them in the corresponding HMQ (according to the frame type) and can notify|
-- the host through an IRQ. |
-- - CPU1 is mainly polling the host to retrieve new payload bytes for production. |
-- When new data is received from the host through a dedicated HMQ, CPU1 puts them |
-- into the Shared Memory for CPU0 to retrieve them and provide them to the |
-- FMC MASTERFIP CORE for serialization. |
-- CPU1 does not need access to the FMC MASTERFIP CORE; however access is possible |
-- for debugging purposes. |
-- |
-- XBAR: |
-- The crossbar between the FMC MASTERFIP CORE and MOCK TURTLE is used so that |
-- CPU0, CPU1 and to the PCIe host can access directly the wbgen2-defined regs |
-- in the FMC MASTERFIP CORE. |
-- Note that to give access to the FMC MASTERFIP CORE to both CPU0 and CPU1, we |
-- could have used the Shared Port of MT, instead of using the Dedicated Ports (DP) |
-- and this crossbar; this though would have also affected (potentially slowed down) |
-- the accesses to the MT Shared Memory. |
-- Note also that as mentioned above CPU1 is only accessing the FMC MASTERFIP CORE |
-- for debugging purposes; the same goes also for the PCIe host. |
-- |
-- CLK, RST: |
-- There is only one clock domain of 100 MHz, in the whole design. The clock is |
-- generated inside the MOCK TURTLE, from the 125 MHz SPEC PLL IC6 output clock |
-- (clk_125m_pllref_p_i,clk_125m_pllref_n_i) and it is used by both MOCK TURTLE CPUs,|
-- by the FMC MASTERFIP CORE and the XBAR. A PCIe reset signal, synchronous to |
-- the 100 MHz clock is also provided by MOCK TURTLE. |
-- |
-- MEMORY MAP AS SEEN FROM PCIe: |
-- 0x00000000 (size: 4 bytes) : SDB signature |
-- 0x00002000 (size: 64 bytes) : VIC |
-- 0x00010000 (size: 644 bytes) : Host access to the FMC MASTERFIP CORE |
-- 0x00020000 (size: 128 kB) : MOCK TURTLE |
-- |-- 0x00020000 : HMQ Global Control Registers |
-- |-- 0x00024000 : HMQ incoming slots (Host->CPUs) |
-- |-- 0x00028000 : HMQ outgoing slots (CPUs->Host) |
-- |-- 0x0002c000 : CPU Control/Status Registers |
-- |-- 0x00030000 : Shared Memory (64 KB) |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Eva Calvo Giraldo (Eva.Calvo.Giraldo@cern.ch) |
-- Tomasz Wlostowski (Tomasz.Wlostowski@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, please download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- std_logic definitions
use IEEE.numeric_std.all; -- conversion functions
library work;
use work.wishbone_pkg.all; -- for the wb_crossbar
use work.spec_node_pkg.all; -- for the spec_node_template definition
use work.wr_node_pkg.all; -- for the spec_node_template configuration
use work.wrn_mqueue_pkg.all; -- for the HMQ
use work.masterFIP_pkg.all; -- for the fmc_masterfip_core definition
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
entity spec_masterfip_pts2 is
generic (g_simulation : boolean := false);
port
(-- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference,
clk_125m_pllref_n_i : in std_logic; -- used in MT to generate 100 MHz
-- GENNUM interface
l_rst_n_i : in std_logic; -- reset from GENNUM (RSTOUT18_N)
gpio_b : inout std_logic_vector(1 downto 0); -- general purpose interface
-- -- PCIe to Local [Inbound Data] - RX
p2l_rdy_o : out std_logic; -- rx buffer full flag
p2l_clkn_i : in std_logic; -- receiver source synch clock-
p2l_clkp_i : in std_logic; -- receiver source synch clock+
p2l_data_i : in std_logic_vector(15 downto 0);-- parallel receive data
p2l_dframe_i : in std_logic; -- receive frame
p2l_valid_i : in std_logic; -- receive data valid
-- -- Inbound Buffer Request/Status
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe write request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe write ready
rx_error_o : out std_logic; -- receive error
-- -- Local to Parallel [Outbound Data] - TX
l2p_data_o : out std_logic_vector(15 downto 0);-- parallel transmit data
l2p_dframe_o : out std_logic; -- transmit data frame
l2p_valid_o : out std_logic; -- transmit data valid
l2p_clkn_o : out std_logic; -- transmitter source synch clock-
l2p_clkp_o : out std_logic; -- transmitter source synch clock+
l2p_edb_o : out std_logic; -- packet termination and discard
-- -- Outbound Buffer Status
l2p_rdy_i : in std_logic; -- tx buffer full flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local read resp data ready
tx_error_i : in std_logic; -- transmit error
vc_rdy_i : in std_logic_vector(1 downto 0); -- channel ready
-- DAC I2C (driven by MT for max stability on the 100 MHz clk)
dac_cs_n_o : out std_logic_vector(1 downto 0); -- 0: select SPEC 25MHz OSC5 VCXO
dac_sclk_o : out std_logic; -- 1: select SPEC 20MHz OSC1 VCXO
dac_din_o : out std_logic;
-- SPEC LEDs
led_green_o : out std_logic; -- blinking with clk_100m_sys
led_red_o : out std_logic; -- active during a PCIe rst, l_rst_n_i
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- FMC signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FMC presence
fmc_prsnt_m2c_n_i : in std_logic; -- FMC presence (used by MT)
-- FMC 1-wire
fmc_onewire_b : inout std_logic; -- temper and unique id
-- WorldFIP bus speed -- 31K25bps: speed_b1=0, speed_b0=0
speed_b0_i : in std_logic; -- 1Mbps : speed_b1=0, speed_b0=1
speed_b1_i : in std_logic; -- 2M5bps : speed_b1=1, speed_b0=0
-- 5Mbps : speed_b1=1, speed_b0=1
-- WorldFIP FielDrive
fd_rstn_o : out std_logic; -- reset
fd_rxcdn_i : in std_logic; -- rx carrier detect
fd_rxd_i : in std_logic; -- rx data
fd_txer_i : in std_logic; -- tx error
fd_wdgn_i : in std_logic; -- tx watchdog
fd_txck_o : out std_logic; -- tx clk
fd_txd_o : out std_logic; -- tx data
fd_txena_o : out std_logic; -- tx enable
-- External synchronisation pulse (input signal and transceiver control)
ext_sync_term_en_o : out std_logic; -- enable 50 Ohm termin of the pulse
ext_sync_dir_o : out std_logic := '0'; -- direction fixed B -> A
ext_sync_oe_n_o : out std_logic := '0'; -- output fixed to enabled
ext_sync_i : in std_logic; -- sync pulse
-- FMC Front panel LEDs: controlled by the MT firmware, updated every macrocycle
led_rx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_tx_act_n_o : out std_logic;
led_tx_err_n_o : out std_logic;
led_sync_act_n_o : out std_logic; -- stays OFF when ext_sync is not used
led_sync_err_n_o : out std_logic; -- stays OFF when ext_sync is not used
-- Test points
tp1_o : out std_logic; -- connected to fd_rxd
tp2_o : out std_logic; -- connected to fd_txd
tp3_o : out std_logic; -- connected to MT led&dbg reg bit 8
tp4_o : out std_logic; -- connected to MT led&dbg reg bit 9
-- To be removed on hw V3
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic);
end spec_masterfip_pts2;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip_pts2 is
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CONSTANTS --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits, each.
-- 8 "out HMQs" from the MT -> towards the host
-- - 0: HMQ from CPU0 with the WorldFIP payloads from periodic consumed variables
-- - 1: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed variables
-- (only for the case of identif variable, scheduled as periodic variable, by radMon app)
-- - 2: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed messages
-- - 3: HMQ from CPU0 with the WorldFIP payloads from periodic consumed diagnostic variables
-- (only for the case of the FIPdiag variable 0x067F)
-- - 4: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed diagnostic variables
-- (aperiodic presence and identification)
-- - 5: HMQ for debugging data from CPU0 and CPU1 towards the host
-- - 6: HMQ for the responses of CPU0 to the commands of the host, see below "in HMQ0"
-- (e.g.: acknowledgement of the configuration???)
-- - 7: HMQ for the responses of CPU1 to the commands of the host, see below "in HMQ1",
-- (e.g.: content of the report variable)
-- 2 "in HMQs" from the host -> towards MT
-- - 0: HMQ towards CPU0 with commands for the bus config, used only at startup (e.g.: HW_RESET,
-- PROGRAM_BA, BA_START, BA_RUNNING)
-- - 1: HMQ towards CPU1 with the payloads for produced WorldFIP frames (variables and messages;
-- CPU1 then puts this data into the Shared Memory for CPU0 to access and put them in the bus)
-- as well as requests for report data, requests for the scheduling of aperiodic traffic
-- (presence/ identification) etc (CPU1 again passes these requests into the Shared Memory).
constant C_HMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 8, -- MT -> towards the host
out_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
2 => (width => 128, entries => 4),
3 => (width => 128, entries => 4),
4 => (width => 128, entries => 4),
5 => (width => 128, entries => 4),
6 => (width => 128, entries => 4),
7 => (width => 128, entries => 4),
others => (0, 0)),
in_slot_count => 2, -- host -> towards MT
in_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
others => (0, 0)));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RMQs not used!
constant C_RMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 0,
out_slot_config => (others => (0, 0)),
in_slot_count => 0,
in_slot_config => (others => (0, 0)));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant C_NODE_CONFIG : t_wr_node_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (98304, 8192, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
-- for the storage of the RT sw running on CPU0
-- and for the macrocycle configuration
hmq_config => C_HMQ_CONFIG,
rmq_config => C_RMQ_CONFIG,
shared_mem_size => 65536); -- in bytes
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant c_WB_SLAVE_STATUS_CSR : integer := 1;
constant C_SLAVE_ADDR : t_wishbone_address_array(1 downto 0):= (
0 => x"00010000",
1 => x"00011000" );
constant C_SLAVE_MASK : t_wishbone_address_array(1 downto 0):= (
0 => x"fffff000",
1 => x"fffff000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- clk, reset
signal clk_100m_sys : std_logic;
signal rst_n_sys : std_logic;
-- Mock Turtle
signal fmc_core_wb_out : t_wishbone_master_out_array(2 downto 0);
signal fmc_core_wb_in : t_wishbone_master_in_array(2 downto 0);
signal fmc_wb_muxed_out : t_wishbone_master_out_array(1 downto 0);
signal fmc_wb_muxed_in : t_wishbone_master_in_array(1 downto 0);
-- SPEC LEDs
signal led_divider : unsigned(22 downto 0);
signal leds : std_logic_vector(31 downto 0);
signal spec_led : std_logic_vector(7 downto 0);
signal fd_txd : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FIXED SIGNALS --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- To be removed on hw V3
-- Note: For the hw v1 signals ext_sync_tst_n_o, adc_prim_conn_n_o and adc_sec_conn_n_o, in order
-- to disable them (that is set them to 'Z'), the ISE setting "Unused IOB pins" is set to
-- "floating", so there is no need to declare them.
adc_1v8_shdn_n_o <= '0'; -- OFF
adc_m5v_shdn_n_o <= '0'; -- OFF
adc_5v_en_n_o <= '1'; -- OFF
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CORE --
---------------------------------------------------------------------------------------------------
cmp_mock_turtle : spec_node_template
generic map
(g_simulation => g_simulation,
g_with_wr_phy => false, -- no White Rabbit support, dah
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
g_system_clock_freq => 100000000, -- both CPUs at 100 MHz
g_wr_node_config => C_NODE_CONFIG)
port map
(clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
rst_n_sys_o => rst_n_sys, -- PCIe rst, synced with clk_sys
clk_sys_o => clk_100m_sys, -- 100 MHz; one clk domain in the whole design
-- PCIe interface
l_rst_n => l_rst_n_i,
gpio => gpio_b,
p2l_rdy => p2l_rdy_o,
p2l_clkn => p2l_clkn_i,
p2l_clkp => p2l_clkp_i,
p2l_data => p2l_data_i,
p2l_dframe => p2l_dframe_i,
p2l_valid => p2l_valid_i,
p_wr_req => p_wr_req_i,
p_wr_rdy => p_wr_rdy_o,
rx_error => rx_error_o,
l2p_data => l2p_data_o,
l2p_dframe => l2p_dframe_o,
l2p_valid => l2p_valid_o,
l2p_clkn => l2p_clkn_o,
l2p_clkp => l2p_clkp_o,
l2p_edb => l2p_edb_o,
l2p_rdy => l2p_rdy_i,
l_wr_rdy => l_wr_rdy_i,
p_rd_d_rdy => p_rd_d_rdy_i,
tx_error => tx_error_i,
vc_rdy => vc_rdy_i,
-- DAC interface
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
dac_cs1_n_o => dac_cs_n_o(0),
dac_cs2_n_o => dac_cs_n_o(1),
-- FMC presence
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_n_i,
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o(0) => fmc_core_wb_out(0), -- access from MT CPU0 at base address 0x100000
dp_master_o(1) => fmc_core_wb_out(1),
dp_master_i(0) => fmc_core_wb_in(0), -- access from MT CPU1 at base address 0x100000
dp_master_i(1) => fmc_core_wb_in(1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => fmc_core_wb_out(2), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => fmc_core_wb_in(2),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
clk_125m_gtp_n_i => '0',
clk_125m_gtp_p_i => '1');
---------------------------------------------------------------------------------------------------
-- XBAR --
---------------------------------------------------------------------------------------------------
-- Crossbar to give access to the fmc_masterFIP_core to CPU0, CPU1 and directly to the PCIe host.
-- Note that to give access to the fmc_masterFIP_core to both CPU0 and CPU1, the SP of MT could
-- have been used instead of the DP and this crossbar; this though would have also affected
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note that in the MT firmware the CPU1 is only accessing the masterfip_leds register for debugging
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_wb_crossbar : xwb_crossbar
generic map
(g_num_masters => 3,
g_num_slaves => 2,
g_registered => true,
g_address => C_SLAVE_ADDR,
g_mask => C_SLAVE_MASK)
port map
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_n_sys,
slave_i => fmc_core_wb_out,
slave_o => fmc_core_wb_in,
master_o => fmc_wb_muxed_out,
master_i => fmc_wb_muxed_in);
---------------------------------------------------------------------------------------------------
-- FMC MASTERFIP CORE --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_core : fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_n_sys,
-- FMC one-wire
onewire_b => fmc_onewire_b,
-- WorldFIP speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- FIELDRIVE
fd_rxcdn_a_i => fd_rxcdn_i,
fd_rxd_a_i => fd_rxd_i,
fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd,
fd_txena_o => fd_txena_o,
-- External Synch
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_a_i => ext_sync_i,
ext_sync_dir_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => open, -- hard-wired to '0'
-- LEDs
leds_o => leds,
-- WISHBONE interface with MT CPU0 and CPU1
wb_adr_i => fmc_wb_muxed_out(0).adr,
wb_dat_i => fmc_wb_muxed_out(0).dat,
wb_stb_i => fmc_wb_muxed_out(0).stb,
wb_we_i => fmc_wb_muxed_out(0).we,
wb_cyc_i => fmc_wb_muxed_out(0).cyc,
wb_sel_i => fmc_wb_muxed_out(0).sel,
wb_dat_o => fmc_wb_muxed_in(0).dat,
wb_ack_o => fmc_wb_muxed_in(0).ack,
wb_stall_o => fmc_wb_muxed_in(0).stall);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- unused WISHBONE signals
fmc_wb_muxed_in(0).err <= '0';
fmc_wb_muxed_in(0).rty <= '0';
fmc_wb_muxed_in(0).int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
led_rx_act_n_o <= leds(0); -- probe on R4
led_rx_err_n_o <= leds(1); -- probe on R8
led_tx_act_n_o <= leds(2); -- probe on R4
led_tx_err_n_o <= leds(3); -- probe on R7
led_sync_act_n_o <= leds(4); -- probe on R1
led_sync_err_n_o <= leds(5); -- probe on R6
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
fd_txd_o <= fd_txd;
tp1_o <= fd_rxd_i;
tp2_o <= fd_txd;
tp3_o <= leds(8);
tp4_o <= leds(9);
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr : entity work.carrier_csr
port map(
rst_n_i => rst_n_sys,
clk_sys_i => clk_100m_sys,
wb_adr_i => fmc_wb_muxed_out(c_WB_SLAVE_STATUS_CSR).adr(3 downto 2), -- fmc_wb_muxed_out.adr is byte address
wb_dat_i => fmc_wb_muxed_out(c_WB_SLAVE_STATUS_CSR).dat,
wb_dat_o => fmc_wb_muxed_in(c_WB_SLAVE_STATUS_CSR).dat,
wb_cyc_i => fmc_wb_muxed_out(c_WB_SLAVE_STATUS_CSR).cyc,
wb_sel_i => fmc_wb_muxed_out(c_WB_SLAVE_STATUS_CSR).sel,
wb_stb_i => fmc_wb_muxed_out(c_WB_SLAVE_STATUS_CSR).stb,
wb_we_i => fmc_wb_muxed_out(c_WB_SLAVE_STATUS_CSR).we,
wb_ack_o => fmc_wb_muxed_in(c_WB_SLAVE_STATUS_CSR).ack,
wb_stall_o => open,
carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE,
carrier_csr_stat_fmc_pres_i => fmc_prsnt_m2c_n_i,
carrier_csr_stat_p2l_pll_lck_i => '1',
carrier_csr_stat_sys_pll_lck_i => '1',
carrier_csr_stat_ddr3_cal_done_i => '1',
carrier_csr_ctrl_led_green_o => open,
carrier_csr_ctrl_led_red_o => open,
carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_rst_fmc0_n_o => open,
carrier_csr_rst_fmc0_n_i => '0',
carrier_csr_rst_fmc0_n_load_o => open
);
fmc_wb_muxed_in(c_WB_SLAVE_STATUS_CSR).err <= '0';
fmc_wb_muxed_in(c_WB_SLAVE_STATUS_CSR).rty <= '0';
fmc_wb_muxed_in(c_WB_SLAVE_STATUS_CSR).int <= '0';
---------------------------------------------------------------------------------------------------
-- SPEC front panel LEDs --
---------------------------------------------------------------------------------------------------
drive_led_clk_sys: process (clk_100m_sys)
begin
if rising_edge(clk_100m_sys) then
if(rst_n_sys = '0') then
spec_led <= "01111111";
led_divider <= (others => '0');
else
led_divider <= led_divider+ 1;
if(led_divider = 0) then
spec_led <= spec_led(6 downto 0) & spec_led(7);
end if;
end if;
end if;
end process;
led_green_o <= spec_led(7);
led_red_o <= not rst_n_sys;
end rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------
\ No newline at end of file
python/fmcmasterfip.py
View file @ cbc84788
......@@ -69,20 +69,17 @@ class fmcmasterfip:
# Carrier specific components
#------------------------------------
# Carrier CSR address
# TODO: recreate
CARRIER_CSR_ADDR = 0x00001200
# Masterfip core registers
MASTERFIP_CORE_ADDR = 0x00010000
CROSSBAR_MAIN = 0x10000
#------------------------------------
# MasterFIP FMC address
# eeprom
# TODO: recreate
MASTERFIP_I2C_EEPROM = CROSSBAR_MAIN + 0x1000
# Masterfip PTS core registers
MASTERFIP_CORE_PTS = 0x00011000
# Masterfip core registers
MASTERFIP_CORE_ADDR = 0x10000
# Carrier CSR address
CARRIER_CSR_ADDR = 0x00012000
# MasterFIP FMC eeprom
MASTERFIP_I2C_EEPROM = 0x00013000
freq_options = [ 31250, 1e6, 25e5, 5e6 ]
......@@ -109,9 +106,6 @@ class fmcmasterfip:
###################################################################
# creation of interfaces to modules controlling external devices
self.fmc_onewire = ow.COpenCoresOneWire(self.carrier, self.MASTERFIP_OW_THERM, 499, 99) #for 40 MHz clock
self.fmc_ds18b20 = ds18b20.CDS18B20(self.fmc_onewire, 0)
self.fmc_sys_i2c = i2c.COpenCoresI2C(self.carrier, self.MASTERFIP_I2C_EEPROM, 199)
self.fmc_eeprom_24aa64 = eeprom_24aa64.C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR)
......@@ -123,7 +117,7 @@ class fmcmasterfip:
###################### firmware initialization ####################
###################################################################
self.verify_bitstream_type();
# self.verify_carrier_status();
self.verify_carrier_status();
self.rst_core()
time.sleep(0.5)
......@@ -143,15 +137,13 @@ class fmcmasterfip:
# Returns FMC unique ID
def get_unique_id(self):
return self.fmc_ds18b20.read_serial_number()
tmp = self.fipcore.read_regname("ds1820_id_msb") << 32;
tmp |= self.fipcore.read_regname("ds1820_id_lsb");
return tmp;
# Returns FMC temperature
def get_temp(self):
serial_number = self.fmc_ds18b20.read_serial_number()
if(serial_number == -1):
return -1
else:
return self.fmc_ds18b20.read_temp(serial_number)
return self.fipcore.read_regname("ds1820_temper");
# write to EEPROM on system i2c bus
def sys_i2c_eeprom_write(self, addr, data):
......@@ -213,19 +205,12 @@ class fmcmasterfip:
# self.send_id_dat(0x7F14)
self.fipcore.write_regname('tx_ctrl', 0 )
time.sleep(0.01)
self.fipcore.write_regname('rstn', 0xCAFE0003)
time.sleep(0.5)
self.fipcore.write_regname('rstn', 0xCAFE0000)
time.sleep(0.5)
self.fipcore.write_regname('rstn', 0xCAFE0003)
self.fipcore.write_regname('rst.core', 1)
time.sleep(1)
def rst_fd(self):
self.fipcore.write_regname('rstn', 0xCAFE0003)
time.sleep(0.5)
self.fipcore.write_regname('rstn', 0xCAFE0001)
time.sleep(0.5)
self.fipcore.write_regname('rstn', 0xCAFE0003)
self.fipcore.write_regname('rst.fd', 1)
time.sleep(1)
......@@ -241,17 +226,14 @@ class fmcmasterfip:
print self.fipcore.read_regname('speed')
return self.freq_options[ self.fipcore.read_regname('speed') ]
# Disable EXT_SYNC test pulse
def disable_ext_sync_tst(self):
self.fipcore.write_regname('ext_sync', 0)
# Send ID_DAT
def send_id_dat(self, varid):
self.fipcore.write_regname('tx_ctrl', 1)
self.fipcore.write_regname('tx_ctrl', 0)
self.fipcore.write_regname('tx_data_ctrl', 0x3)
self.fipcore.write_regname('tx_data_reg1', varid)
self.fipcore.write_regname('tx_payld_ctrl', 0x3)
self.fipcore.write_regname('tx_payld_reg1', varid)
self.fipcore.write_regname('tx_ctrl', 0x202)
......@@ -259,9 +241,9 @@ class fmcmasterfip:
def read_rp_dat(self):
rx_stat = self.fipcore.read_regname('rx_stat')
rx_data_ctrl = self.fipcore.read_regname('rx_data_ctrl')
rx_data_reg1 = self.fipcore.read_regname('rx_data_reg1')
rx_data_reg2 = self.fipcore.read_regname('rx_data_reg2')
rx_data_reg3 = self.fipcore.read_regname('rx_data_reg3')
rx_data_ctrl = self.fipcore.read_regname('rx_payld_ctrl')
rx_data_reg1 = self.fipcore.read_regname('rx_payld_reg1')
rx_data_reg2 = self.fipcore.read_regname('rx_payld_reg2')
rx_data_reg3 = self.fipcore.read_regname('rx_payld_reg3')
rx_data = rx_data_reg3 << 32*2 | rx_data_reg2 << 32*1 | rx_data_reg1 << 32*0
return [ rx_stat, rx_data_ctrl, rx_data ]
python/regs/masterfip_pts_csr.htm 0 → 100644
View file @ cbc84788
<HTML>
<HEAD>
<TITLE>masterfip_pts_csr</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
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</HEAD>
<BODY>
<h1 class="heading">masterfip_pts_csr</h1>
<h3>FMC masterFIP PTS registers</h3>
<p>Wishbone slave for FMC masterFIP PTS</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">rst</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">ext sync</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">ext sync raw input</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">PTS options</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">fieldrive status</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">fieldrive tx error counter</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#RST">rst</a>
</td>
<td class="td_code">
mfpts_rst
</td>
<td class="td_code">
RST
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#EXT_SYNC">ext sync</a>
</td>
<td class="td_code">
mfpts_ext_sync
</td>
<td class="td_code">
EXT_SYNC
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#EXT_SYNC_RAW_INPUT">ext sync raw input</a>
</td>
<td class="td_code">
mfpts_ext_sync_raw_input
</td>
<td class="td_code">
EXT_SYNC_RAW_INPUT
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#TX_CORRUPT">PTS options</a>
</td>
<td class="td_code">
mfpts_tx_corrupt
</td>
<td class="td_code">
TX_CORRUPT
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#FD">fieldrive status</a>
</td>
<td class="td_code">
mfpts_fd
</td>
<td class="td_code">
FD
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#FD_TXERR_CNT">fieldrive tx error counter</a>
</td>
<td class="td_code">
mfpts_fd_txerr_cnt
</td>
<td class="td_code">
FD_TXERR_CNT
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>rst:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_rst_core_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[2:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>ext sync:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_ext_sync_term_en_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_ext_sync_dir_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_ext_sync_oe_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_ext_sync_output_value_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_ext_sync_p_cnt_rst_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_ext_sync_fpga_io_dir_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>ext sync raw input:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_ext_sync_raw_input_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>PTS options:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_tx_corrupt_enable_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>fieldrive status:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_fd_wdgn_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_fd_wdgn_latch_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_fd_cd_n_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_fd_txer_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>fieldrive tx error counter:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mfpts_fd_txerr_cnt_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="RST"></a>
<h3><a name="sect_3_1">3.1. rst</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
mfpts_rst
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
RST
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
software reset of the masterFIP core
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
CORE
</td>
</tr>
</table>
<ul>
<li><b>
CORE
</b>[<i>write-only</i>]: reset of the masterFIP core
<br>write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;<br> note: there is no need to clear the bit before writing another '1'
</ul>
<a name="EXT_SYNC"></a>
<h3><a name="sect_3_2">3.2. ext sync</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
mfpts_ext_sync
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EXT_SYNC
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FPGA_IO_DIR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
P_CNT_RST
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
OUTPUT_VALUE
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
OE
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DIR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TERM_EN
</td>
</tr>
</table>
<ul>
<li><b>
TERM_EN
</b>[<i>read/write</i>]: termination enable
<br>write 0: disable 50ohms termination of the external sync pulse<br> write 1: enable 50ohms termination of the external sync pulse
<li><b>
DIR
</b>[<i>read/write</i>]: transceiver direction
<br>write 0: normal operation (input)<br> write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector
<li><b>
OE
</b>[<i>read/write</i>]: transceiver output enable
<br> This line is negated in the GW in order to correctly control the relay<br> write 1: the external sync pulse arrives to the FPGA<br> write 0: the external sync pulse does not arrive to the FPGA
<li><b>
OUTPUT_VALUE
</b>[<i>read/write</i>]: External sync output value (when buffer is switched)
<br>Value outputted then sync is set to output direction
<li><b>
P_CNT_RST
</b>[<i>read/write</i>]: pulses counter reset
<br>resets the pulses counter
<li><b>
FPGA_IO_DIR
</b>[<i>read/write</i>]: FPGA IO direction
<br>Direction of FPGA IO
</ul>
<a name="EXT_SYNC_RAW_INPUT"></a>
<h3><a name="sect_3_3">3.3. ext sync raw input</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
mfpts_ext_sync_raw_input
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EXT_SYNC_RAW_INPUT
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_RAW_INPUT
</td>
</tr>
</table>
<ul>
<li><b>
EXT_SYNC_RAW_INPUT
</b>[<i>read-only</i>]: ext_sync_raw_input
<br>External sync input value. Only valid whrn direction is set to input
</ul>
<a name="TX_CORRUPT"></a>
<h3><a name="sect_3_4">3.4. PTS options</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
mfpts_tx_corrupt
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TX_CORRUPT
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ENABLE
</td>
</tr>
</table>
<ul>
<li><b>
ENABLE
</b>[<i>read/write</i>]: enable
<br>When corrupt is set to 1 serial tx data is forced to 0.
</ul>
<a name="FD"></a>
<h3><a name="sect_3_5">3.5. fieldrive status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
mfpts_fd
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FD
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TXER
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
CD_N
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
WDGN_LATCH
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
WDGN
</td>
</tr>
</table>
<ul>
<li><b>
WDGN
</b>[<i>read-only</i>]: fd watchdog
<br>fd_wdgn input from the fieldrive chip
<li><b>
WDGN_LATCH
</b>[<i>read-only</i>]: fd watchdog latched
<br>Active watchdog state is latched. Register is reseted by reset core and reset fd
<li><b>
CD_N
</b>[<i>read-only</i>]: fd carrier detect
<br>CDn input from the fieldrive chip
<li><b>
TXER
</b>[<i>read-only</i>]: fd transmitter error
<br>fd_txer input from the fieldrive chip
</ul>
<a name="FD_TXERR_CNT"></a>
<h3><a name="sect_3_6">3.6. fieldrive tx error counter</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
mfpts_fd_txerr_cnt
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FD_TXERR_CNT
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x14
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
FD_TXERR_CNT[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
FD_TXERR_CNT[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
FD_TXERR_CNT[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
FD_TXERR_CNT[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FD_TXERR_CNT
</b>[<i>read-only</i>]: fieldrive tx error counter
<br>Number of TX Errors. Counter is reset by macrocycle, core reset and fd reset
</ul>
</BODY>
</HTML>
python/regs/masterfip_pts_csr.py 0 → 100644
View file @ cbc84788
# Register definitions for slave core: FMC masterFIP PTS registers
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# * Created : Mon Mar 20 16:55:05 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
#
addr = {
'rst' : [ 0x0, 0xffffffff, "w"],
'ext_sync' : [ 0x1, 0xffffffff, "rw"],
'ext_sync.term_en' : [ 0x1, 0x1, "rw"],
'ext_sync.dir' : [ 0x1, 0x2, "rw"],
'ext_sync.oe' : [ 0x1, 0x4, "rw"],
'ext_sync.output_value' : [ 0x1, 0x8, "rw"],
'ext_sync.p_cnt_rst' : [ 0x1, 0x100, "rw"],
'ext_sync.fpga_io_dir' : [ 0x1, 0x200, "rw"],
'ext_sync_raw_input' : [ 0x2, 0xffffffff, "r"],
'tx_corrupt' : [ 0x3, 0xffffffff, "rw"],
'fd' : [ 0x4, 0xffffffff, "r"],
'fd.wdgn' : [ 0x4, 0x1, "r"],
'fd.wdgn_latch' : [ 0x4, 0x2, "r"],
'fd.cd_n' : [ 0x4, 0x4, "r"],
'fd.txer' : [ 0x4, 0x8, "r"],
'fd_txerr_cnt' : [ 0x5, 0xffffffff, "r"],
'':[0,0]
}
python/test.c deleted 100644 → 0
View file @ e1f89d31
void main(){
printf( "Hello word");
printf( "sdf asdkfds ")
}
python/test02.py
View file @ cbc84788
......@@ -233,8 +233,8 @@ def test_txerr( dut, box, maxtries = 50 ):
dut.fipcore.write_regname('tx_ctrl', 1)
dut.fipcore.write_regname('tx_ctrl', 0)
dut.fipcore.write_regname('tx_data_ctrl', 0x3)
dut.fipcore.write_regname('tx_data_reg1', 0x7F14)
dut.fipcore.write_regname('tx_payld_ctrl', 0x3)
dut.fipcore.write_regname('tx_payld_reg1', 0x7F14)
dut.fipcore.write_regname('tx_ctrl', 0x202)
time.sleep(0.5)
......@@ -286,8 +286,8 @@ def test_wdgn( dut ):
dut.fipcore.write_regname('tx_ctrl', 1)
dut.fipcore.write_regname('tx_ctrl', 0)
dut.fipcore.write_regname('tx_data_ctrl', 0x3)
dut.fipcore.write_regname('tx_data_reg1', 0x7F14)
dut.fipcore.write_regname('tx_payld_ctrl', 0x3)
dut.fipcore.write_regname('tx_payld_reg1', 0x7F14)
dut.fipcore.write_regname('tx_ctrl', 0x202)
wait_transmission_termination(dut, 100, 2 )
......@@ -305,8 +305,8 @@ def test_wdgn( dut ):
dut.fipcore.write_regname('tx_ctrl', 1)
dut.fipcore.write_regname('tx_ctrl', 0)
dut.fipcore.write_regname('tx_data_ctrl', 0x3)
dut.fipcore.write_regname('tx_data_reg1', 0x7F14)
dut.fipcore.write_regname('tx_payld_ctrl', 0x3)
dut.fipcore.write_regname('tx_payld_reg1', 0x7F14)
dut.fipcore.write_regname('tx_ctrl', 0xFFF02)
......
python/utilities.py
View file @ cbc84788
......@@ -13,7 +13,7 @@ INFO = True
WARRNING = True
CRITICAL = True
FIRMWARE_PATH ='gateware/syn/spec/spec_top_fmc_masterfip.bin'
FIRMWARE_PATH ='gateware/syn/spec/spec_masterfip_pts.bin'
TOPDIRNAME ="fmcmasterfip"
test03_outputpath ='/tmp/'
......
scripts/wbscript.sh
View file @ cbc84788
......@@ -35,3 +35,11 @@ top=`echo "$prg" | sed 's/fmcmasterfip\/.*/fmcmasterfip/'`
"$top/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb"
"$top/scripts/wbgen2" \
-D "$top/python/regs/masterfip_pts_csr.htm" \
-P "$top/python/regs/masterfip_pts_csr.py" \
-l vhdl \
-V "$top/gateware/rtl/wbgen/masterfip_pts_csr.vhd" \
"$top/gateware/rtl/wbgen/masterfip_pts_csr.wb"
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