Update rtl code for spi_slave, mt_profip_translator. Now sim is OK but MISO line is shifted by 1 in HW/SW test

SPI slave changed: generates busy flag, load input data with data valid input. mt_profip_translator changes in read fsm

Updated spi_slave and mt_profip_translator. Working in Simulation up to 5MHz spi clock and 62.5MHz system clock

CDC between SPI and FIFOs are now between 125MHz and 62.5MHz. Also modifications in top level so we can use front panel pins for HW debug. Not working properly yet

finished with writing to RMQ. Also corner case when we write less than we expect fixed. Reading phase is not yet finished.

WR added to .gitmodules, needed for SPEC convention base. HMQ out and notify IRQs added in the top level

Minor changes did now that serializable will not be used in the testbench + changes in .tcl file used for synthesis

Changes in the configuration of MT, new tcl script added with some option enabled so that the design can fit and not have timing errors with 45T spartan 6 FPGA