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MasterFIP - Gateware
Commit 7afaf80f authored by kblantos's avatar kblantos
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Design now supports latest mockturtle, still place&route errors

parent e7bb1c46
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Showing with 465 additions and 23373 deletions
gn4124-core @ 3799226c
Subproject commit c629364388453726da401909b5154306ab4e6930
Subproject commit 3799226c5e7bc75489c0a787006963e067ce46bb
rtl/Manifest.py 0 → 100644
View file @ 7afaf80f
files = [
"decr_counter.vhd",
"fmc_masterFIP_core.vhd",
"incr_counter.vhd",
"masterFIP_pkg.vhd",
"masterfip_rx.vhd",
"masterfip_tx.vhd",
"masterfip_wbgen2_csr.vhd",
"masterfip_wbgen2_pkg.vhd",
"wf_mfp_package.vhd",
]
rtl/fmc_masterFIP_core.vhd
View file @ 7afaf80f
......@@ -155,10 +155,9 @@ use work.masterfip_wbgen2_pkg.all;
use work.masterfip_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
--use work.wrcore_pkg.all;
use work.genram_pkg.all;
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
-- Entity declaration for fmc_masterFIP_core
......@@ -305,7 +304,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE rst: generation of a pulse 1 x WorldFIP-clk-cycles long
cmp_fd_rst_generate: gc_dyn_extend_pulse
cmp_fd_rst_generate: entity work.gc_dyn_extend_pulse
generic map(g_len_width => c_PERIODS_COUNTER_LGTH)
port map
(clk_i => clk_i,
......@@ -321,7 +320,7 @@ begin
---------------------------------------------------------------------------------------------------
-- WBGEN2 REGS FROM/TO MOCK TURTLE --
---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: masterfip_wbgen2_csr
cmp_masterfip_csr: entity work.masterfip_wbgen2_csr
port map
(rst_n_i => rst_n_i,
clk_sys_i => clk_i,
......@@ -346,7 +345,7 @@ begin
ext_sync_term_en_o <= reg_from_mt.ext_sync_ctrl_term_en_o;
-- input synchronizer of the ext_sync_a_i signal
cmp_ext_sync_sync: gc_sync_ffs
cmp_ext_sync_sync: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -355,7 +354,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_ext_sync_deglitch: gc_glitch_filt
cmp_ext_sync_deglitch: entity work.gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
port map -- Note that the filter adds a 100 ns delay to the ext_sync signal
......@@ -366,7 +365,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- rising edge detection on the deglitched signal
cmp_ext_sync_deglitch_p_detect: gc_sync_ffs
cmp_ext_sync_deglitch_p_detect: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -375,7 +374,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter of the number of rising edges
cmp_ext_sync_p_cnt:incr_counter
cmp_ext_sync_p_cnt : entity work.incr_counter
generic map(g_counter_lgth => 32) -- for the fastest macrocycle of 20ms, the counter
-- can keep counting for 2.7 years
port map
......@@ -401,7 +400,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the macrocycle time;
-- the macrocycle length (counter top) should be set once upon the application startup
cmp_macrocycle_time_cnt: decr_counter
cmp_macrocycle_time_cnt : entity work.decr_counter
generic map(width => g_width-1)
port map
(clk_i => clk_i,
......@@ -422,7 +421,7 @@ begin
-- counter counting the number of macrocycles;
-- being a 32-bit counter, for the fastest application of 20 ms macrocycle, the counter can
-- keep counting for 2.7 years; when it fills up it would restart from 0.
cmp_macrocycles_cnt: incr_counter
cmp_macrocycles_cnt: entity work.incr_counter
generic map(g_counter_lgth => g_width)
port map
(clk_i => clk_i,
......@@ -442,7 +441,7 @@ begin
-- and before the transmission of a new frame.
-- turnaround counter
cmp_turnaround_cnt: decr_counter
cmp_turnaround_cnt: entity work.decr_counter
generic map(width => 31)
port map
(clk_i => clk_i,
......@@ -464,7 +463,7 @@ begin
-- (tx_completed_p) or after the reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p) for the
-- case of a RP_DAT_MSG that would be followed by RP_FIN.
cmp_silence_cnt: decr_counter
cmp_silence_cnt: entity work.decr_counter
generic map(width => 31)
port map
(clk_i => clk_i,
......@@ -482,7 +481,7 @@ begin
-- MASTERFIP RX --
---------------------------------------------------------------------------------------------------
-- Note that the deglitching of the fd_rxd_a_i takes place inside the masterfip_rx unit.
cmp_masterfip_rx: masterfip_rx
cmp_masterfip_rx: entity work.masterfip_rx
port map
(clk_i => clk_i,
rst_i => core_rst,
......@@ -560,7 +559,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter of frames with crc errors since the startup or a core reset (not on every macrocycle)
cmp_rx_crc_err_cnt: incr_counter
cmp_rx_crc_err_cnt: entity work.incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
......@@ -573,7 +572,7 @@ begin
-- MASTERFIP TX --
---------------------------------------------------------------------------------------------------
cmp_masterfip_tx: masterfip_tx
cmp_masterfip_tx: entity work.masterfip_tx
port map
(clk_i => clk_i,
rst_i => tx_rst,
......@@ -634,7 +633,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- input synchronizer of the fd_wdgn_a_i signal
cmp_fd_wdgn_sync: gc_sync_ffs
cmp_fd_wdgn_sync: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -645,7 +644,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_fd_wdg_deglitch: gc_glitch_filt
cmp_fd_wdg_deglitch: entity work.gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
......@@ -657,7 +656,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- edge detection
cmp_fd_wdgn_deglitch_p_detect: gc_sync_ffs
cmp_fd_wdgn_deglitch_p_detect: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -687,7 +686,7 @@ begin
-- is inactive.
-- input synchronizer of the fd_rxcdn_a_i signal
cmp_fd_rxcdn_sync: gc_sync_ffs
cmp_fd_rxcdn_sync: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -698,7 +697,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- deglitch filter
cmp_fd_rxcd_deglitch: gc_glitch_filt
cmp_fd_rxcd_deglitch: entity work.gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
......@@ -718,7 +717,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- input synchronizer of the fd_txer_a_i signal
cmp_fd_txer_sync: gc_sync_ffs
cmp_fd_txer_sync: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -727,7 +726,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_fd_txer_deglitch: gc_glitch_filt
cmp_fd_txer_deglitch: entity work.gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
......@@ -739,7 +738,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- edge detection on the fd_txer_filt signal
cmp_fd_txer_deglitch_p_detect: gc_sync_ffs
cmp_fd_txer_deglitch_p_detect: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -748,7 +747,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the number of fd_txer_p
cmp_fd_txer_cnt:incr_counter
cmp_fd_txer_cnt : entity work.incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
......@@ -786,7 +785,7 @@ begin
-- Note that a temperature reading is provided every second, with the first one a couple of sec
-- after the board power-up/ reset.
cmp_onewire: gc_ds182x_interface
cmp_onewire: entity work.gc_ds182x_interface
generic map (freq => C_QUARTZ_FREQ_MHZ_INT)
port map
(clk_i => clk_i,
......@@ -799,7 +798,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- pps generator based on the 100 MHz clk
cmp_pps_gen: wf_decr_counter
cmp_pps_gen: entity work.wf_decr_counter
generic map(g_counter_lgth => C_1SEC_CNT_LGTH)
port map
(uclk_i => clk_i,
......
rtl/masterFIP_pkg.vhd
View file @ 7afaf80f
......@@ -14,7 +14,7 @@
-- |
-- Description Definitions of constants, types, entities related to the interface between the |
-- fmc_masterfip_core and the Mock Turtle. |
-- Note that a different package, the wf_package, is used for the WorldFIP specific |
-- Note that a different package, the wf_mfp_package, is used for the WorldFIP specific |
-- constant, types, entities and for the clock constants. |
-- |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
......@@ -43,7 +43,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wf_package.all; -- WorldFIP specifics package
use work.wf_mfp_package.all; -- WorldFIP specifics package
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
......@@ -81,7 +81,7 @@ package masterFIP_pkg is
-- 263.
constant C_MAX_FRAME_WORDS : integer := 67;
constant C_MAX_FRAME_BYTES : integer := 266;
constant C_MFP_MAX_FRAME_BYTES : integer := 266;
constant C_FRAME_WORDS_CNT_LGTH : integer := 7; -- counter overflows after 128 words = 512 bytes
-- for normal rx operation it should not exceed
-- 67 words; for normal tx operation it should
......@@ -105,7 +105,7 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filters --
---------------------------------------------------------------------------------------------------
-- constant C_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
-- constant C_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_mfp_package
---------------------------------------------------------------------------------------------------
......@@ -241,4 +241,4 @@ package masterFIP_pkg is
end masterFIP_pkg;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
rtl/masterfip_rx.vhd
View file @ 7afaf80f
......@@ -97,7 +97,7 @@ use IEEE.math_real.all;
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
......@@ -158,7 +158,7 @@ entity masterfip_rx is port(
rx_fss_received_p_o : out std_logic; -- pulse upon FSS detection (ID/ RP_DAT)
rx_bytes_num_err_o : out std_logic); -- active after the reception of > C_MAX_FRAME_BYTES bytes
rx_bytes_num_err_o : out std_logic); -- active after the reception of > C_MFP_MAX_FRAME_BYTES bytes
-- and until a rst_i OR rst_rx_i
end entity masterfip_rx;
......@@ -200,7 +200,7 @@ begin
-- Deserializer as in the nanoFIP project --
---------------------------------------------------------------------------------------------------
cmp_rx_deglitcher: wf_rx_deglitcher
cmp_rx_deglitcher: entity work.wf_rx_deglitcher
port map(
uclk_i => clk_i,
nfip_rst_i => rx_rst_i,
......@@ -213,7 +213,7 @@ begin
fd_rxd_filt_r_edge_p <= rxd_filt_edge_p and (not fd_rxd_filt_f_edge_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_deserializer: wf_rx_deserializer
cmp_rx_deserializer: entity work.wf_rx_deserializer
port map(
uclk_i => clk_i,
nfip_rst_i => rst_i,
......@@ -238,7 +238,7 @@ begin
rx_fss_crc_fes_ok_p_o <= rx_fss_crc_fes_ok_p;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_osc: wf_rx_osc
cmp_rx_osc: entity work.wf_rx_osc
port map(
uclk_i => clk_i,
rate_i => speed_i,
......@@ -256,7 +256,7 @@ begin
---------------------------------------------------------------------------------------------------
-- bytes counter --
---------------------------------------------------------------------------------------------------
cmp_rx_bytes_cnt: incr_counter
cmp_rx_bytes_cnt: entity work.incr_counter
generic map(g_counter_lgth => C_FRAME_BYTES_CNT_LGTH)
port map(
clk_i => clk_i,
......@@ -271,7 +271,7 @@ begin
---------------------------------------------------------------------------------------------------
-- rx bytes exceeded C_MAX_FRAME_BYTES --
-- rx bytes exceeded C_MFP_MAX_FRAME_BYTES --
---------------------------------------------------------------------------------------------------
-- indication that the rx counter exceeded the max expected number of bytes
p_rx_bytes_num_err: process (clk_i)
......@@ -280,7 +280,7 @@ begin
if rst_i = '1' or rx_rst_i = '1' then
rx_bytes_num_err_o <= '0';
else
if unsigned(rx_byte_index) > C_MAX_FRAME_BYTES then
if unsigned(rx_byte_index) > C_MFP_MAX_FRAME_BYTES then
rx_bytes_num_err_o <= '1';
end if;
end if;
......@@ -393,4 +393,4 @@ end architecture struc;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
rtl/masterfip_tx.vhd
View file @ 7afaf80f
......@@ -96,7 +96,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
......@@ -328,4 +328,4 @@ end architecture struc;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
rtl/masterfip_wbgen2_csr.vhd
View file @ 7afaf80f
......@@ -3,8 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Created : 05/31/18 17:36:43
-- Version : 0x00020100
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -157,7 +157,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
masterfip_ver_id_int <= "00000000000000100000000000000000";
masterfip_ver_id_int <= "00000000000000100000000100000000";
masterfip_rst_core_int <= '0';
masterfip_rst_fd_int <= '0';
masterfip_led_rx_act_int <= '0';
......@@ -2036,3 +2036,4 @@ begin
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
rtl/masterfip_wbgen2_pkg.vhd
View file @ 7afaf80f
This diff is collapsed.
rtl/wf_package.vhd → rtl/wf_mfp_package.vhd
View file @ 7afaf80f
......@@ -7,16 +7,16 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_PACKAGE |
-- wf_mfp_package |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_package.vhd |
-- File wf_mfp_package.vhd |
-- |
-- Description Definitions of constants, types, entities, functions related to WorldFIP |
-- serialization and deserialization; the package is essential for all the modules |
-- coming from the nanoFIP design. |
-- As in the masterFIP design the clk is 100 MHz and in the nanoFIP 40 MHz it was |
-- necessary to have a new wf_package. In principle the nanoFIP design could have |
-- necessary to have a new wf_mfp_package. In principle the nanoFIP design could have |
-- been modified to accept generics rather than constants, however as it is a stable |
-- design it was decided to keep it as it is and use for synthesis this package |
-- rather than the one coming with the nanoFIP submodule. |
......@@ -53,9 +53,9 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Package declaration for wf_package
-- Package declaration for wf_mfp_package
--=================================================================================================
package wf_package is
package wf_mfp_package is
---------------------------------------------------------------------------------------------------
......@@ -387,13 +387,13 @@ end component wf_rx_osc;
end wf_package;
end wf_mfp_package;
--=================================================================================================
-- package body
--=================================================================================================
package body wf_package is
package body wf_mfp_package is
---------------------------------------------------------------------------------------------------
......@@ -420,10 +420,10 @@ package body wf_package is
end wf_package;
end wf_mfp_package;
--=================================================================================================
-- package end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
syn/spec/Manifest.py 0 → 100644
View file @ 7afaf80f
action = "synthesis"
target = "xilinx"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
#syn_top = "spec_masterfip_mt_urv"
#syn_project = "spec_masterfip_mt_urv.xise"
#top_module = "spec_masterfip_mt_urv"
syn_top = "spec_masterfip_mt"
syn_project = "spec_masterfip_mt.xise"
syn_module = "spec_masterfip_mt"
syn_tool = "ise"
modules = {
"local" : [
"../../top/spec",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"ssh://git@gitlab.cern.ch:7999/coht/mockturtle.git",
"git://ohwr.org/cern-fip/nanofip/nanofip-gateware.git",
],
}
syn/spec/spec_masterfip_mt.par deleted 100644 → 0
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syn/spec/spec_masterfip_mt.syr deleted 100644 → 0
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syn/spec/spec_masterfip_mt.twr deleted 100644 → 0
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syn/spec/spec_masterfip_mt.xise deleted 100644 → 0
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syn/spec/spec_masterfip_mt_map.mrp deleted 100644 → 0
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top/spec/Manifest.py 0 → 100644
View file @ 7afaf80f
files = [
"spec_masterfip_mt.ucf",
# "spec_masterfip_mt_urv.vhd",
"spec_masterfip_mt.vhd",
"spec_reset_gen.vhd",
]
modules = {
"local" : [
"../../rtl",
],
}
top/spec/spec_masterfip_mt.ucf
View file @ 7afaf80f
......@@ -154,20 +154,6 @@ NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0 P2V5: SPEC DAC
#----------------------------------------
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
NET "dac_cs_n_o[1]" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
......@@ -265,13 +251,18 @@ NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
#NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
NET "cmp_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
#NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
NET "cmp_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
#NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
NET "cmp_GN4124_Core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/06/30
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
#NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
NET "cmp_GN4124_Core/cmp_clk_in/feedback" TNM_NET = cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_mock_turtle_gen_with_gennum_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" 20 ns HIGH 50%;
top/spec/spec_reset_gen.vhd 0 → 100644
View file @ 7afaf80f
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_reset_gen |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_reset_gen.vhd |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- SOLDERPAD LICENSE |
-- Copyright CERN 2014-2018 |
-- ------------------------------------ |
-- Copyright and related rights are licensed under the Solderpad Hardware License, Version 2.0 |
-- (the "License"); you may not use this file except in compliance with the License. |
-- You may obtain a copy of the License at http://solderpad.org/licenses/SHL-2.0. |
-- Unless required by applicable law or agreed to in writing, software, hardware and materials |
-- distributed under this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR |
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language |
-- governing permissions and limitations under the License. |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
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