- extended all pulses entering the WRNC

- added fd_txena signal to WRNC csr - cleanup

- extended all pulses entering the WRNC
- added fd_txena signal to WRNC csr - cleanup
9ba467f9 · Evangelia Gousiou · bf7aaca0 · 9ba467f9 · 9ba467f9 · 9ba467f9
Commit 9ba467f9 authored Oct 13, 2015 by Evangelia Gousiou
10 changed files
--- a/rtl/fmc_masterFIP_core.vhd
+++ b/rtl/fmc_masterFIP_core.vhd
--- a/rtl/fmc_masterfip_csr.vhd
+++ b/rtl/fmc_masterfip_csr.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fmc_masterfip_csr.vhd
 -- Author         : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created        : 10/07/15 16:39:58
+-- Created        : 10/13/15 12:13:25
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
@@ -82,6 +82,8 @@ entity fmc_masterfip_csr is
    mf_tx_stat_stop_i                        : in     std_logic;
 -- Port for std_logic_vector field: 'tx current byte' in reg: 'tx status'
    mf_tx_stat_byte_index_i                  : in     std_logic_vector(8 downto 0);
+-- Port for BIT field: 'tx enable' in reg: 'tx status'
+    mf_tx_stat_ena_i                         : in     std_logic;
 -- Port for BIT field: 'fd watchdog' in reg: 'fieldrive status'
    mf_fd_wdgn_i                             : in     std_logic;
 -- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
@@ -876,6 +878,7 @@ begin
            end if;
            rddata_reg(0) <= mf_tx_stat_stop_i;
            rddata_reg(16 downto 8) <= mf_tx_stat_byte_index_i;
+            rddata_reg(24) <= mf_tx_stat_ena_i;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
@@ -890,7 +893,6 @@ begin
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
-            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
@@ -1982,6 +1984,7 @@ begin
  mf_tx_ctrl_bytes_num_o <= mf_tx_ctrl_bytes_num_int;
 -- tx ended
 -- tx current byte
+-- tx enable
 -- fd watchdog
 -- fd transmitter error
 -- rx rst

--- a/rtl/masterFIP_pkg.vhd
+++ b/rtl/masterFIP_pkg.vhd
--- a/rtl/masterfip_rx.vhd
+++ b/rtl/masterfip_rx.vhd
@@ -119,6 +119,10 @@ entity masterfip_rx is port(
    rx_ctrl_byte_o        : out std_logic_vector(7 downto 0); -- frame CTRL byte
+    rx_pdu_byte_o        : out std_logic_vector(7 downto 0); -- frame CTRL byte
+    rx_lgth_byte_o        : out std_logic_vector(7 downto 0); -- frame CTRL byte
    rx_frame_o            : out rx_frame_t;                   -- frame DATA bytes
                                                              -- structure with 66 words of 32-bit each
                                                              -- this represents the max length of a frame

--- a/rtl/wbgen/fmc_masterfip_csr.wb
+++ b/rtl/wbgen/fmc_masterfip_csr.wb
@@ -380,6 +380,16 @@ peripheral {
 	  align = 8;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
+    };
+	field {
+      name = "tx enable";
+      description = "fieldrive fd_txena signal; serializer is active putting bits to the bus";
+      prefix = "ena";
+      type = BIT;
+	  align = 8;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
    };	
  };

--- a/sim/spec/data_vectors/masterFIP_test.vec
+++ b/sim/spec/data_vectors/masterFIP_test.vec
@@ -43,16 +43,16 @@ wait   %d20
 ----- CHECK COUNTERS FUNCTINALITY -----
 -- macrocycle cnt start
-wr 0000000000030018 F 80007D00
+--wr 0000000000030018 F 80001D00
-wait   %d20
+--wait   %d20
 -- turnar counter top
-wr 000000000003001C F 000007D0
+--wr 000000000003001C F 000007D0
-wait   %d20
+--wait   %d20
 -- silen counter top
-wr 0000000000030020 F 00000FA0
+--wr 0000000000030020 F 00000FA0
-wait   %d20
+--wait   %d20

--- a/sim/spec/testbench/tb_masterFIP.vhd
+++ b/sim/spec/testbench/tb_masterFIP.vhd
@@ -397,8 +397,8 @@ begin
 		  ext_sync_i        => ext_sync,
-        speed_b0_i        => '0',
+        speed_b0_i        => '1',
-        speed_b1_i        => '1',
+        speed_b1_i        => '0',
        fd_rxcdn_i        => fd_rxcdn,
        fd_rxd_i          => fd_rxd,
@@ -607,8 +607,9 @@ begin
        wait for nanoFIP_clk_period/2;
    end process;
-    ext_sync   <= '1' after 8500 ns, '0' after 8580 ns;
+    --ext_sync   <= '1' after 8500   ns, '0' after 8580   ns,
+    --              '1' after 194000 ns, '0' after 194080 ns,
+    --              '1' after 565151 ns, '0' after 565231 ns;
    rst_n               <= RSTOUT18n;
    GPIO(0)             <= irq_p;

--- a/syn/spec_wrnode/spec_masterfip_wrnode.xise
+++ b/syn/spec_wrnode/spec_masterfip_wrnode.xise
--- a/top/spec/spec_masterFIP.vhd
+++ b/top/spec/spec_masterFIP.vhd
@@ -434,7 +434,7 @@ begin
 ---------------------------------------------------------------------------------------------------
 --                                         masterFIP BOARD                                       --
 ---------------------------------------------------------------------------------------------------
-  cmp_masterFIP_mezz : fmc_masterFIP_core
+  cmp_masterFIP_core : fmc_masterFIP_core
  generic map
    (g_span             => 32,
     g_width            => 32,
@@ -467,7 +467,7 @@ begin
     adc_m5v_shdn_n_o   => adc_m5v_shdn_n_o,
     adc_5v_en_n_o      => adc_5v_en_n_o,
    -- WISHBONE interface with the GN4124 core
-     wb_adr_i           => "00" & cnx_master_out(c_WB_SLAVE_MASTERFIP).adr(31 downto 2),
+     wb_adr_i           => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
     wb_dat_i           => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
     wb_stb_i           => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
     wb_we_i            => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
@@ -487,30 +487,33 @@ begin
  fd_txena_o <= fd_txena;
  -- LEDs font panel
-  led_tx_err_n_o <= fd_txer_i;
+  -- led_tx_err_n_o <= fd_txer_i;
-  led_tx_act_n_o <= fd_txena;
+  -- led_tx_act_n_o <= fd_txena;
-  led_rx_err_n_o <= rx_err;
+  -- led_rx_err_n_o <= rx_err;
-  led_rx_act_n_o <= rx_act;
+  -- led_rx_act_n_o <= rx_act;
-    cmp_rx_err_extend_p : gc_extend_pulse
+    -- cmp_rx_err_extend_p : gc_extend_pulse
-    generic map (
+    -- generic map (
-      g_width => 50000)
+      -- g_width => 50000)
-    port map (
+    -- port map (
-      clk_i      => clk_40m_sys,
+      -- clk_i      => clk_40m_sys,
-      rst_n_i    => rst_sys_n,
+      -- rst_n_i    => rst_sys_n,
-      pulse_i    => aux(0),
+      -- pulse_i    => aux(0),
-      extended_o => rx_err);
+      -- extended_o => rx_err);
-    cmp_rx_act_extend_p : gc_extend_pulse
+    -- cmp_rx_act_extend_p : gc_extend_pulse
-    generic map (
+    -- generic map (
-      g_width => 50000)
+      -- g_width => 50000)
-    port map (
+    -- port map (
-      clk_i      => clk_40m_sys,
+      -- clk_i      => clk_40m_sys,
-      rst_n_i    => rst_sys_n,
+      -- rst_n_i    => rst_sys_n,
-      pulse_i    => aux(1),
+      -- pulse_i    => aux(1),
-      extended_o => rx_act);      
+      -- extended_o => rx_act);      
+  led_tx_err_n_o <= aux(5);
+  led_tx_act_n_o <= aux(0);
+  led_rx_err_n_o <= aux(2);
+  led_rx_act_n_o <= aux(6);
 ---------------------------------------------------------------------------------------------------
 --                    Carrier 1-wire MASTER DS18B20 (thermometer + unique ID)                    --
 ---------------------------------------------------------------------------------------------------

--- a/top/spec_wrnode/spec_top.vhd
+++ b/top/spec_wrnode/spec_top.vhd
@@ -340,11 +340,12 @@ begin
  fd_txena_o <= fd_txena;
+  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  
  -- LEDs front panel
  --led_tx_err_n_o <= fd_txer_i;
-  led_tx_act_n_o <= fd_txena;
+  -- led_tx_act_n_o <= fd_txena;
-  led_rx_err_n_o <= rx_err;
+  -- led_rx_err_n_o <= rx_err;
-  led_rx_act_n_o <= rx_act;
+  -- led_rx_act_n_o <= rx_act;
  cmp_rx_err_extend_p : gc_extend_pulse
    generic map (
@@ -364,26 +365,28 @@ begin
      pulse_i    => aux(1),
      extended_o => rx_act);
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  -- clk_40m_sys_drive_led: process (clk_sys)
-  clk_40m_sys_drive_led: process (clk_sys)
+  -- begin
-  begin
+    -- if rising_edge(clk_sys) then
-    if rising_edge(clk_sys) then
+      -- if(rst_n_sys = '0') then
-      if(rst_n_sys = '0') then
+        -- led_clk_40m_aux     <= "01111111";
-        led_clk_40m_aux     <= "01111111";
+        -- led_clk_40m_divider <= (others => '0');
-        led_clk_40m_divider <= (others => '0');
+      -- else
-      else
+        -- led_clk_40m_divider <= led_clk_40m_divider+ 1;
-        led_clk_40m_divider <= led_clk_40m_divider+ 1;
+        -- if(led_clk_40m_divider = 0) then
-        if(led_clk_40m_divider = 0) then
+          -- led_clk_40m_aux   <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
-          led_clk_40m_aux   <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
+        -- end if;
-        end if;
+      -- end if;
-      end if;
+    -- end if;
-    end if;
+  -- end process;
-  end process;
+  -- --  --  --  --  --
-  --  --  --  --  --
+  -- led_tx_err_n_o <= led_clk_40m_aux(0);
-  led_tx_err_n_o <= led_clk_40m_aux(0);
+  led_tx_err_n_o <= aux(5);
+  led_tx_act_n_o <= aux(0);
+  led_rx_err_n_o <= aux(2);
+  led_rx_act_n_o <= aux(6);