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MasterFIP - Gateware
Commit bf7aaca0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wrnode: fixed address shift in CSR block, reverted mqueue sizes

parent eaf3913c
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Showing with 1284 additions and 1293 deletions
rtl/Manifest.py
View file @ bf7aaca0
......@@ -3,7 +3,6 @@ files=[ "carrier_info.vhd",
"fmc_masterFIP_core.vhd",
"fmc_masterfip_csr.vhd",
"fmc_masterfip_eic.vhd",
"fmc_masterFIP_mezz.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"masterFIP_pkg.vhd",
......
rtl/fmc_masterFIP_core.vhd
View file @ bf7aaca0
......@@ -178,7 +178,7 @@ begin
-- wishbone
rst_n_i => rst_n,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(7 downto 0),
wb_adr_i => wb_adr_i(9 downto 2),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
......
syn/spec_wrnode/spec_masterfip_wrnode.xise
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top/spec_wrnode/spec_top.vhd
View file @ bf7aaca0
......@@ -164,20 +164,20 @@ architecture rtl of spec_top is
-- 3) a small outgoing queue (8 entries x 128 words) for receiving command replies
-- (CPU to host)
constant c_hmq_config : t_wrn_mqueue_config :=
constant c_hmq_config : t_wrn_mqueue_config :=
(
out_slot_count => 4,
out_slot_config => (
0 => (width => 128, entries => 8), -- control CPU 0 (to host)
1 => (width => 128, entries => 8), -- control CPU 1 (to host)
2 => (width => 16, entries => 128), -- log CPU 0
3 => (width => 16, entries => 128), -- log CPU 1
0 => (width => 128, entries => 4), -- control CPU 0 (to host)
1 => (width => 128, entries => 4), -- control CPU 1 (to host)
2 => (width => 128, entries => 4), -- log CPU 0
3 => (width => 128, entries => 4), -- log CPU 1
others => (0, 0)),
in_slot_count => 2,
in_slot_config => (
0 => (width => 32, entries => 8), -- control CPU 0 (from host)
1 => (width => 32, entries => 8), -- control CPU 1 (from host)
0 => (width => 128, entries => 4), -- control CPU 0 (from host)
1 => (width => 128, entries => 4), -- control CPU 1 (from host)
others => (0, 0)
)
);
......@@ -191,12 +191,12 @@ architecture rtl of spec_top is
(
out_slot_count => 1,
out_slot_config => (
0 => (width => 128, entries => 16), -- TDC remote out
0 => (width => 128, entries => 4), -- TDC remote out
others => (0, 0)),
in_slot_count => 1,
in_slot_config => (
0 => (width => 128, entries => 16), -- FD remote in
0 => (width => 128, entries => 4), -- FD remote in
others => (0, 0)
)
......@@ -206,7 +206,7 @@ architecture rtl of spec_top is
(
app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (32768, 32768, 0, 0, 0, 0, 0, 0),
cpu_memsizes => (65536, 65536, 0, 0, 0, 0, 0, 0),
hmq_config => c_hmq_config,
rmq_config => c_rmq_config,
shared_mem_size => 65536
......
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