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MasterFIP - Gateware
Commit 9ba467f9 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- extended all pulses entering the WRNC 

- added fd_txena signal to WRNC csr
- cleanup
parent bf7aaca0
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Showing with 1671 additions and 1563 deletions
rtl/fmc_masterFIP_core.vhd
View file @ 9ba467f9
......@@ -115,54 +115,53 @@ entity fmc_masterFIP_core is
architecture rtl of fmc_masterFIP_core is
-- resets
constant c_RST_UNLOCK_VALUE : std_logic_vector(15 downto 0) := x"cafe";
signal rst_n, core_rst, core_rst_n, rx_rst, rx_rst_p : std_logic;
signal core_rstn_tmp, fd_rstn_tmp, rstn_lock_wr : std_logic;--_vector (0 downto 0);
signal core_host_rst, fd_host_rst, core_host_rstn, fd_host_rstn : std_logic;
signal rstn_lock : std_logic_vector(15 downto 0);
-- speed
signal speed_host : std_logic_vector(1 downto 0);
signal speed_ok : std_logic;
constant c_RST_UNLOCK_VALUE : std_logic_vector(15 downto 0) := x"cafe";
signal rst_n, core_rst, core_rst_n, rx_rst, rx_rst_p : std_logic;
signal core_rstn_tmp, fd_rstn_tmp, rstn_lock_wr, fd_host_rstn : std_logic;
signal core_host_rst, fd_host_rst, core_host_rstn : std_logic;
signal rstn_lock : std_logic_vector(15 downto 0);
-- ext pulse
signal ext_sync_p : std_logic;
signal ext_sync_p : std_logic;
-- counters
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector(30 downto 0);
signal macrocyc_sw_load, turnar_sw_load, silen_sw_load : std_logic;
signal macrocyc_sw_load_p, turnar_sw_load_p, silen_sw_load_p : std_logic;
signal macrocyc_cnt, turnar_cnt, silen_cnt : std_logic_vector(30 downto 0);
signal macrocyc_cnt_zero_p : std_logic;
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector(30 downto 0);
signal macrocyc_host_load, turnar_host_load, silen_host_load : std_logic;
signal macrocyc_host_load_p, turnar_host_load_p : std_logic;
signal silen_host_load_p : std_logic;
signal macrocyc_cnt, turnar_cnt, silen_cnt : std_logic_vector(30 downto 0);
signal macrocyc_cnt_zero_p : std_logic;
-- tx
signal tx_completed_p, tx_rst, tx_start, tx_start_p : std_logic;
signal tx_frame : tx_frame_t;
signal tx_ctrl_byte : std_logic_vector(7 downto 0);
signal tx_bytes_num, tx_byte_index : std_logic_vector(8 downto 0); -- up to 263 bytes
signal tx_completed_p, tx_completed, tx_start, tx_start_p : std_logic;
signal tx_rst, tx_rst_p, fd_txd, fd_txck : std_logic;
signal tx_frame : tx_frame_t;
signal tx_ctrl_byte : std_logic_vector(7 downto 0);
signal tx_bytes_num, tx_byte_index : std_logic_vector(8 downto 0); -- up to 263 bytes
-- rx
signal rx_fss_received_p, rx_fss_received, rx_fss_crc_fes_ok_p : std_logic;
signal rx_frame_ok_p, rx_crc_wrong_p, rx_byte_ready_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_data_bytes : std_logic_vector(8 downto 0); -- up to 263 bytes
signal rx_fss_received_p, rx_fss_received : std_logic;
signal rx_fss_crc_fes_ok_p, rx_frame_ok_p, rx_frame_ok : std_logic;
signal rx_crc_wrong_p, rx_crc_wrong, rx_byte_ready_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_data_bytes : std_logic_vector(8 downto 0); -- up to 263 bytes
-- Chipscope
-- component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
-- CLK : in std_logic;
-- TRIG0 : in std_logic_vector(31 downto 0);
-- TRIG1 : in std_logic_vector(31 downto 0);
-- TRIG2 : in std_logic_vector(31 downto 0);
-- TRIG3 : in std_logic_vector(31 downto 0));
-- end component;
-- component chipscope_icon
-- port (
-- CONTROL0 : inout std_logic_vector (35 downto 0));
-- end component;
-- signal CONTROL : std_logic_vector(35 downto 0);
-- signal CLK : std_logic;
-- signal TRIG0 : std_logic_vector(31 downto 0);
-- signal TRIG1 : std_logic_vector(31 downto 0);
-- signal TRIG2 : std_logic_vector(31 downto 0);
-- signal TRIG3 : std_logic_vector(31 downto 0);
-- chipscope
-- component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
-- CLK : in std_logic;
-- TRIG0 : in std_logic_vector(31 downto 0);
-- TRIG1 : in std_logic_vector(31 downto 0);
-- TRIG2 : in std_logic_vector(31 downto 0);
-- TRIG3 : in std_logic_vector(31 downto 0));
-- end component;
-- component chipscope_icon
-- port (CONTROL0 : inout std_logic_vector(35 downto 0));
-- end component;
-- signal CONTROL : std_logic_vector(35 downto 0);
-- signal CLK : std_logic;
-- signal TRIG0 : std_logic_vector(31 downto 0);
-- signal TRIG1 : std_logic_vector(31 downto 0);
-- signal TRIG2 : std_logic_vector(31 downto 0);
-- signal TRIG3 : std_logic_vector(31 downto 0);
--=================================================================================================
......@@ -188,8 +187,8 @@ begin
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
-- resets
mf_rstn_core_o => core_rstn_tmp, -- reset has to be confirmed with lock word
mf_rstn_fd_o => fd_rstn_tmp, -- reset has to be confirmed with lock word
mf_rstn_core_o => core_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
mf_rstn_fd_o => fd_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
mf_rstn_lock_o => rstn_lock,
mf_rstn_lock_wr_o => rstn_lock_wr,
-- adc supplies
......@@ -209,32 +208,33 @@ begin
mf_speed_i(0) => speed_b0_i,
-- counters outputs
mf_macrocyc_lgth_o => macrocyc_lgth,
mf_macrocyc_start_o => macrocyc_sw_load,
mf_turnar_lgth_o => turnar_lgth,
mf_turnar_start_o => turnar_sw_load,
mf_silen_lgth_o => silen_lgth,
mf_silen_start_o => silen_sw_load,
mf_macrocyc_start_o => macrocyc_host_load, -- optional counters loading through the host
mf_turnar_start_o => turnar_host_load,
mf_silen_start_o => silen_host_load,
-- counters inputs
mf_macrocyc_time_cnt_i => (macrocyc_cnt_zero_p or macrocyc_sw_load_p) & macrocyc_cnt,
mf_turnar_time_cnt_i => (tx_completed_p or turnar_sw_load_p) & turnar_cnt,
mf_silen_time_cnt_i => (tx_completed_p or silen_sw_load_p) & silen_cnt,
mf_macrocyc_time_cnt_i => (macrocyc_cnt_zero_p or macrocyc_host_load_p) & macrocyc_cnt,
mf_turnar_time_cnt_i => (tx_completed_p or turnar_host_load_p) & turnar_cnt,
mf_silen_time_cnt_i => (tx_completed_p or silen_host_load_p) & silen_cnt,
-- tx control
mf_tx_ctrl_rst_o => tx_rst, -- tx rst have to convert to pulse
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame have to convert to pulse
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize
mf_tx_ctrl_rst_o => tx_rst, -- tx rst; then converted to 1-tick-long pulse
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame; then converted to 1-tick-long pulse
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start
-- tx status
mf_tx_stat_stop_i => tx_completed_p, -- pulse upon the end of delivery of a frame
mf_tx_stat_byte_index_i => tx_byte_index,
mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog
mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr
mf_tx_stat_stop_i => tx_completed, -- 16x25ns long pulse upon the end of delivery of a frame
mf_tx_stat_byte_index_i => tx_byte_index, -- index of current byte being serialized
mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer
mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog, signal comes from the FIELDRIVE
mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr, signal comes from the FIELDRIVE
-- rx control/status
mf_rx_ctrl_rst_o => rx_rst, -- note: this is not a pulse
-- rx status
mf_rx_stat_pream_ok_i => rx_fss_received,
mf_rx_stat_frame_ok_i => rx_frame_ok_p, -- have to extend the pulse
mf_rx_stat_frame_err_i => '0',
mf_rx_stat_frame_ok_i => rx_frame_ok,
mf_rx_stat_frame_err_i => rx_crc_wrong,
mf_rx_stat_frame_err_code_i => "000",
mf_rx_stat_bytes_num_i => rx_data_bytes,
mf_rx_stat_bytes_num_i => rx_byte_index, -- rx_data_bytes,
-- rx data
mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg1_i => rx_frame(0),
......@@ -371,8 +371,8 @@ begin
mf_tx_data_reg64_o => tx_frame(63),
mf_tx_data_reg65_o => tx_frame(64),
mf_tx_data_reg66_o => tx_frame(65));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
---------------------------------------------------------------------------------------------------
-- resets --
......@@ -380,7 +380,7 @@ begin
rst_n <= not rst_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reset generation
p_sw_reset : process(clk_i)
p_host_reset : process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n = '0') then
......@@ -423,18 +423,18 @@ begin
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => macrocyc_cnt_zero_p or macrocyc_sw_load_p or ext_sync_p,
counter_load_i => macrocyc_cnt_zero_p or macrocyc_host_load_p or ext_sync_p,
counter_top_i => macrocyc_lgth,
counter_o => macrocyc_cnt,
counter_is_zero_o => macrocyc_cnt_zero_p);
cmp_macrocyc_sw_load_p_detect: gc_sync_ffs
cmp_macrocyc_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => macrocyc_sw_load,
ppulse_o => macrocyc_sw_load_p);
data_i => macrocyc_host_load,
ppulse_o => macrocyc_host_load_p);
---------------------------------------------------------------------------------------------------
......@@ -445,18 +445,18 @@ begin
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_sw_load_p,
counter_load_i => tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_host_load_p,
counter_top_i => turnar_lgth,
counter_o => turnar_cnt,
counter_is_zero_o => open);
turnar_sw_load_p_detect: gc_sync_ffs
turnar_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => turnar_sw_load,
ppulse_o => turnar_sw_load_p);
data_i => turnar_host_load,
ppulse_o => turnar_host_load_p);
--------------------------------------------------------------------------------------------------
-- silence counter --
......@@ -469,18 +469,18 @@ begin
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or silen_sw_load_p,
counter_load_i => tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or silen_host_load_p,
counter_top_i => silen_lgth,
counter_o => silen_cnt,
counter_is_zero_o => open);
cmp_silen_sw_load_p_detect: gc_sync_ffs
cmp_silen_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => silen_sw_load,
ppulse_o => silen_sw_load_p);
data_i => silen_host_load,
ppulse_o => silen_host_load_p);
--------------------------------------------------------------------------------------------------
......@@ -507,9 +507,29 @@ begin
clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => rx_fss_received_p,
extended_o => rx_fss_received);
extended_o => rx_fss_received);
-- extension of the rx_frame_ok_p so as to ensure capturing by the wrnc
cmp_rx_frame_ok_extend_p : gc_extend_pulse
generic map (
g_width => 16)
port map (
clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => rx_frame_ok_p,
extended_o => rx_frame_ok);
-- extension of the rx_crc_wrong_p so as to ensure capturing by the wrnc
cmp_rx_crc_wrong_extend_p : gc_extend_pulse
generic map (
g_width => 16)
port map (
clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => rx_crc_wrong_p,
extended_o => rx_crc_wrong);
rx_rst_pulse_detect: gc_sync_ffs
cmp_rx_rst_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
......@@ -525,7 +545,7 @@ begin
port map(
clk_40m_i => clk_i,
rst_i => core_rst,
speed_i => "01",
speed_i => speed_b1_i & speed_b0_i,
fd_rxd_a_i => fd_rxd_i,
rx_rst_i => rx_rst_p or fd_txena, -- reset from the WRNC or reset while transmitting
-------------------------------------------------------------
......@@ -552,8 +572,8 @@ begin
cmp_masterfip_tx: masterfip_tx
port map(
clk_40m_i => clk_i,
rst_i => (core_rst or tx_rst),
speed_i => "01",
rst_i => (core_rst or tx_rst_p),
speed_i => speed_b1_i & speed_b0_i,
tx_bytes_num_i => tx_bytes_num,
tx_start_p_i => tx_start_p,
tx_frame_i => tx_frame,
......@@ -561,64 +581,109 @@ begin
-------------------------------------------------------------
tx_byte_index_o => tx_byte_index,
tx_end_p_o => tx_completed_p,
tx_data_o => fd_txd_o,
tx_data_o => fd_txd,
tx_enable_o => fd_txena,
tx_clk_o => fd_txck_o);
tx_clk_o => fd_txck);
-------------------------------------------------------------
fd_txena_o <= fd_txena;
fd_txd_o <= fd_txd;
fd_txck_o <= fd_txck;
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
-- create 1-clk-tick long pulse upon tx_rst
cmp_tx_rst_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => tx_rst,
ppulse_o => tx_rst_p);
-- extension of the tx_completed_p so as to ensure capturing by the wrnc
cmp_tx_extend_p : gc_extend_pulse
generic map (
g_width => 16)
port map (
clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => tx_completed_p,
extended_o => tx_completed);
---------------------------------------------------------------------------------------------------
-- aux --
---------------------------------------------------------------------------------------------------
aux_o(7) <= rx_fss_received_p;
aux_o(6) <= rx_fss_received;
aux_o(5) <= rx_frame_ok;
aux_o(4) <= rx_byte_ready_p;
aux_o(3) <= tx_rst;
aux_o(2) <= tx_completed_p;
aux_o(1) <= tx_start;
aux_o(0) <= rx_frame_ok_p;
aux_o <= "00000" & rx_crc_wrong_p & rx_byte_ready_p & tx_start_p;
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
-- TRIG0(7 downto 0) <= rx_byte;
-- TRIG0(8) <= rx_byte_ready_p;
-- TRIG0(16 downto 9) <= byte_to_tx;
-- TRIG0(17) <= tx_start_p;
-- TRIG0(18) <= rx_fss_crc_fes_ok_p;
-- TRIG0(19) <= start_tx_p;
-- TRIG0(20) <= tx_completed_p;
-- TRIG0(21) <= rx_fss_crc_fes_ok_p;
-- TRIG0(22) <= rx_fss_received_p;
-- TRIG0(23) <= rx_crc_wrong_p;
-- TRIG1(7 downto 0) <= tx_byte_index;
-- TRIG1(15 downto 8) <= rx_byte_index;
-- TRIG1(16) <= irq_p;
-- TRIG0(16) <= start_from_fpga;
-- TRIG0(24 downto 17) <= retrig_nb_offset(7 downto 0);
-- TRIG0(31 downto 25) <= clk_i_cycles_offset(6 downto 0);
--
-- TRIG1(30 downto 0) <= acam_tstamp1(30 downto 0);
-- TRIG1(31) <= acam_tstamp1_ok_p;
--
-- TRIG2(31 downto 0) <= utc(31 downto 0);
--
-- TRIG3(0) <= tdc_in_fpga_1_i;
-- TRIG3(1) <= roll_over_incr_recent;
-- TRIG3(2) <= wrabbit_tai_p_i;
-- TRIG3(31 downto 3) <= current_retrig_nb(28 downto 0);
-- TRIG0(8 downto 0) <= tx_bytes_num;
-- TRIG0(9) <= tx_start;
-- TRIG0(10) <= tx_start_p;
-- TRIG0(18 downto 11) <= tx_ctrl_byte;
-- TRIG0(27 downto 19) <= tx_byte_index;
-- TRIG0(28) <= tx_completed_p;
-- TRIG0(29) <= fd_txena;
-- TRIG0(30) <= fd_txd;
-- TRIG0(31) <= fd_txck;
-- TRIG1 <= tx_frame(0);
-- TRIG2(8 downto 0) <= rx_byte_index;
-- TRIG2(9) <= rx_fss_received_p;
-- TRIG2(10) <= rx_byte_ready_p;
-- TRIG2(18 downto 11) <= rx_byte;
-- TRIG2(26 downto 19) <= rx_ctrl_byte;
-- TRIG2(27) <= rx_frame_ok_p;
-- TRIG2(28) <= rx_crc_wrong_p;
-- TRIG2(29) <= core_rst;
-- TRIG2(31 downto 30) <= speed_b1_i & speed_b0_i;
-- TRIG3 <= rx_frame(0);
--TRIG0(17) <= tx_start_p;
--TRIG0(18) <= rx_fss_crc_fes_ok_p;
--TRIG0(19) <= start_tx_p;
--TRIG0(21) <= rx_fss_crc_fes_ok_p;
--TRIG0(22) <= rx_fss_received_p;
--TRIG0(23) <= rx_crc_wrong_p;
--TRIG1(15 downto 8) <= rx_byte_index;
--TRIG0(16) <= start_from_fpga;
--TRIG0(24 downto 17) <= retrig_nb_offset(7 downto 0);
--TRIG0(31 downto 25) <= clk_i_cycles_offset(6 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
......
rtl/fmc_masterfip_csr.vhd
View file @ 9ba467f9
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/07/15 16:39:58
-- Created : 10/13/15 12:13:25
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -82,6 +82,8 @@ entity fmc_masterfip_csr is
mf_tx_stat_stop_i : in std_logic;
-- Port for std_logic_vector field: 'tx current byte' in reg: 'tx status'
mf_tx_stat_byte_index_i : in std_logic_vector(8 downto 0);
-- Port for BIT field: 'tx enable' in reg: 'tx status'
mf_tx_stat_ena_i : in std_logic;
-- Port for BIT field: 'fd watchdog' in reg: 'fieldrive status'
mf_fd_wdgn_i : in std_logic;
-- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
......@@ -876,6 +878,7 @@ begin
end if;
rddata_reg(0) <= mf_tx_stat_stop_i;
rddata_reg(16 downto 8) <= mf_tx_stat_byte_index_i;
rddata_reg(24) <= mf_tx_stat_ena_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -890,7 +893,6 @@ begin
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -1982,6 +1984,7 @@ begin
mf_tx_ctrl_bytes_num_o <= mf_tx_ctrl_bytes_num_int;
-- tx ended
-- tx current byte
-- tx enable
-- fd watchdog
-- fd transmitter error
-- rx rst
......
rtl/masterFIP_pkg.vhd
View file @ 9ba467f9
......@@ -177,126 +177,131 @@ package masterFIP_pkg is
component fmc_masterfip_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
mf_rstn_core_o : out std_logic;
mf_rstn_fd_o : out std_logic;
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
mf_rstn_core_o : out std_logic;
mf_rstn_fd_o : out std_logic;
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
mf_adc_1v8_shdn_n_o : out std_logic;
mf_adc_m5v_shdn_n_o : out std_logic;
mf_adc_5v_en_n_o : out std_logic;
mf_ext_sync_term_en_o : out std_logic;
mf_ext_sync_dir_o : out std_logic;
mf_ext_sync_oe_o : out std_logic;
mf_ext_sync_tst_n_o : out std_logic;
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
mf_adc_1v8_shdn_n_o : out std_logic;
mf_adc_m5v_shdn_n_o : out std_logic;
mf_adc_5v_en_n_o : out std_logic;
mf_ext_sync_term_en_o : out std_logic;
mf_ext_sync_dir_o : out std_logic;
mf_ext_sync_oe_o : out std_logic;
mf_ext_sync_tst_n_o : out std_logic;
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
mf_bus_term_en_n_o : out std_logic;
mf_speed_i : in std_logic_vector(1 downto 0);
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
mf_macrocyc_start_o : out std_logic;
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
mf_turnar_start_o : out std_logic;
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
mf_silen_start_o : out std_logic;
mf_macrocyc_time_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_time_cnt_i : in std_logic_vector(31 downto 0);
mf_silen_time_cnt_i : in std_logic_vector(31 downto 0);
mf_bus_term_en_n_o : out std_logic;
mf_speed_i : in std_logic_vector(1 downto 0);
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
mf_macrocyc_start_o : out std_logic;
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
mf_turnar_start_o : out std_logic;
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
mf_silen_start_o : out std_logic;
mf_macrocyc_time_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_time_cnt_i : in std_logic_vector(31 downto 0);
mf_silen_time_cnt_i : in std_logic_vector(31 downto 0);
mf_tx_ctrl_rst_o : out std_logic;
mf_tx_ctrl_start_o : out std_logic;
mf_tx_ctrl_bytes_num_o : out std_logic_vector(8 downto 0);
mf_tx_stat_stop_i : in std_logic;
mf_tx_stat_byte_index_i : in std_logic_vector(8 downto 0);
mf_fd_wdgn_i : in std_logic;
mf_fd_txer_i : in std_logic;
mf_tx_stat_ena_i : in std_logic;
mf_fd_wdgn_i : in std_logic;
mf_fd_txer_i : in std_logic;
mf_rx_ctrl_rst_o : out std_logic;
mf_rx_stat_pream_ok_i : in std_logic;
mf_rx_stat_frame_ok_i : in std_logic;
mf_rx_stat_frame_err_i : in std_logic;
mf_rx_stat_frame_err_code_i : in std_logic_vector(2 downto 0);
mf_rx_stat_bytes_num_i : in std_logic_vector(8 downto 0);
mf_rx_data_ctrl_i : in std_logic_vector(7 downto 0);
mf_rx_data_reg1_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg2_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg3_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg4_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg5_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg6_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg7_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg8_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg9_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg10_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg11_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg12_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg13_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg14_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg15_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg16_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg17_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg18_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg19_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg20_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg21_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg22_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg23_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg24_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg25_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg26_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg27_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg28_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg29_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg30_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg31_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg32_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg33_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg34_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg35_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg36_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg37_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg38_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg39_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg40_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg41_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg42_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg43_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg44_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg45_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg46_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg47_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg48_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg49_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg50_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg51_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg52_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg53_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg54_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg55_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg56_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg57_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg58_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg59_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg60_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg61_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg62_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg63_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg64_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg65_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg66_i : in std_logic_vector(31 downto 0);
mf_rx_data_ctrl_i : in std_logic_vector(7 downto 0);
mf_rx_data_reg1_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg2_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg3_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg4_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg5_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg6_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg7_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg8_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg9_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg10_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg11_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg12_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg13_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg14_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg15_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg16_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg17_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg18_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg19_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg20_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg21_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg22_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg23_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg24_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg25_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg26_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg27_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg28_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg29_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg30_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg31_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg32_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg33_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg34_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg35_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg36_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg37_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg38_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg39_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg40_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg41_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg42_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg43_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg44_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg45_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg46_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg47_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg48_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg49_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg50_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg51_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg52_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg53_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg54_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg55_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg56_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg57_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg58_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg59_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg60_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg61_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg62_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg63_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg64_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg65_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg66_i : in std_logic_vector(31 downto 0);
mf_tx_data_ctrl_o : out std_logic_vector(7 downto 0);
mf_tx_data_reg1_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg2_o : out std_logic_vector(31 downto 0);
......@@ -480,7 +485,7 @@ package masterFIP_pkg is
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector (8 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
tx_byte_index_o : out std_logic_vector (8 downto 0);
tx_end_p_o : out std_logic;
......
rtl/masterfip_rx.vhd
View file @ 9ba467f9
......@@ -119,6 +119,10 @@ entity masterfip_rx is port(
rx_ctrl_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_pdu_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_lgth_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_frame_o : out rx_frame_t; -- frame DATA bytes
-- structure with 66 words of 32-bit each
-- this represents the max length of a frame
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 9ba467f9
......@@ -380,6 +380,16 @@ peripheral {
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx enable";
description = "fieldrive fd_txena signal; serializer is active putting bits to the bus";
prefix = "ena";
type = BIT;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......
sim/spec/data_vectors/masterFIP_test.vec
View file @ 9ba467f9
......@@ -43,16 +43,16 @@ wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
wr 0000000000030018 F 80007D00
wait %d20
--wr 0000000000030018 F 80001D00
--wait %d20
-- turnar counter top
wr 000000000003001C F 000007D0
wait %d20
--wr 000000000003001C F 000007D0
--wait %d20
-- silen counter top
wr 0000000000030020 F 00000FA0
wait %d20
--wr 0000000000030020 F 00000FA0
--wait %d20
......
sim/spec/testbench/tb_masterFIP.vhd
View file @ 9ba467f9
......@@ -397,8 +397,8 @@ begin
ext_sync_i => ext_sync,
speed_b0_i => '0',
speed_b1_i => '1',
speed_b0_i => '1',
speed_b1_i => '0',
fd_rxcdn_i => fd_rxcdn,
fd_rxd_i => fd_rxd,
......@@ -607,8 +607,9 @@ begin
wait for nanoFIP_clk_period/2;
end process;
ext_sync <= '1' after 8500 ns, '0' after 8580 ns;
--ext_sync <= '1' after 8500 ns, '0' after 8580 ns,
-- '1' after 194000 ns, '0' after 194080 ns,
-- '1' after 565151 ns, '0' after 565231 ns;
rst_n <= RSTOUT18n;
GPIO(0) <= irq_p;
......
syn/spec_wrnode/spec_masterfip_wrnode.xise
View file @ 9ba467f9
This source diff could not be displayed because it is too large. You can view the blob instead.
top/spec/spec_masterFIP.vhd
View file @ 9ba467f9
......@@ -434,7 +434,7 @@ begin
---------------------------------------------------------------------------------------------------
-- masterFIP BOARD --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_mezz : fmc_masterFIP_core
cmp_masterFIP_core : fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
......@@ -467,7 +467,7 @@ begin
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
-- WISHBONE interface with the GN4124 core
wb_adr_i => "00" & cnx_master_out(c_WB_SLAVE_MASTERFIP).adr(31 downto 2),
wb_adr_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
......@@ -487,30 +487,33 @@ begin
fd_txena_o <= fd_txena;
-- LEDs font panel
led_tx_err_n_o <= fd_txer_i;
led_tx_act_n_o <= fd_txena;
led_rx_err_n_o <= rx_err;
led_rx_act_n_o <= rx_act;
-- led_tx_err_n_o <= fd_txer_i;
-- led_tx_act_n_o <= fd_txena;
-- led_rx_err_n_o <= rx_err;
-- led_rx_act_n_o <= rx_act;
cmp_rx_err_extend_p : gc_extend_pulse
generic map (
g_width => 50000)
port map (
clk_i => clk_40m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(0),
extended_o => rx_err);
cmp_rx_act_extend_p : gc_extend_pulse
generic map (
g_width => 50000)
port map (
clk_i => clk_40m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(1),
extended_o => rx_act);
-- cmp_rx_err_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 50000)
-- port map (
-- clk_i => clk_40m_sys,
-- rst_n_i => rst_sys_n,
-- pulse_i => aux(0),
-- extended_o => rx_err);
-- cmp_rx_act_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 50000)
-- port map (
-- clk_i => clk_40m_sys,
-- rst_n_i => rst_sys_n,
-- pulse_i => aux(1),
-- extended_o => rx_act);
led_tx_err_n_o <= aux(5);
led_tx_act_n_o <= aux(0);
led_rx_err_n_o <= aux(2);
led_rx_act_n_o <= aux(6);
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
---------------------------------------------------------------------------------------------------
......
top/spec_wrnode/spec_top.vhd
View file @ 9ba467f9
......@@ -340,11 +340,12 @@ begin
fd_txena_o <= fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- LEDs front panel
--led_tx_err_n_o <= fd_txer_i;
led_tx_act_n_o <= fd_txena;
led_rx_err_n_o <= rx_err;
led_rx_act_n_o <= rx_act;
-- led_tx_act_n_o <= fd_txena;
-- led_rx_err_n_o <= rx_err;
-- led_rx_act_n_o <= rx_act;
cmp_rx_err_extend_p : gc_extend_pulse
generic map (
......@@ -364,26 +365,28 @@ begin
pulse_i => aux(1),
extended_o => rx_act);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_40m_sys_drive_led: process (clk_sys)
begin
if rising_edge(clk_sys) then
if(rst_n_sys = '0') then
led_clk_40m_aux <= "01111111";
led_clk_40m_divider <= (others => '0');
else
led_clk_40m_divider <= led_clk_40m_divider+ 1;
if(led_clk_40m_divider = 0) then
led_clk_40m_aux <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
end if;
end if;
end if;
end process;
-- -- -- -- --
led_tx_err_n_o <= led_clk_40m_aux(0);
-- clk_40m_sys_drive_led: process (clk_sys)
-- begin
-- if rising_edge(clk_sys) then
-- if(rst_n_sys = '0') then
-- led_clk_40m_aux <= "01111111";
-- led_clk_40m_divider <= (others => '0');
-- else
-- led_clk_40m_divider <= led_clk_40m_divider+ 1;
-- if(led_clk_40m_divider = 0) then
-- led_clk_40m_aux <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
-- end if;
-- end if;
-- end if;
-- end process;
-- -- -- -- -- --
-- led_tx_err_n_o <= led_clk_40m_aux(0);
led_tx_err_n_o <= aux(5);
led_tx_act_n_o <= aux(0);
led_rx_err_n_o <= aux(2);
led_rx_act_n_o <= aux(6);
......
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