Scalable MAROC Charge Sensitive Readout
Project description
The Scalable MAROC Charge Sensitive Readout couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP.
Top view of single MAROC board, with 1000Base-T SFP
inserted.*
Bottom view of single MAROC board. 64 inputs through 150 pin Samtec
QTS75 connector*
Main Features
- MAROC3 ASIC with 64 channels. Adjustable gain amplifiers. Adjustable shaping time. 12 bit ADC
- Xilinx Spartan-3 FPGA
- Read out using IPBus over Gigabit Ethernet.
- Two-edge pluggable to increase channel count. 16 differential pairs
on each connector.
- Connected boards can share clock , trigger and Ethernet link
- Two Gigabit serial links with SFP cages
- Two Gigabit serial links connected via SATA connectors
- Single +12V supply
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Project information
- Circuit schematic capture and PCB layout (Using Cadence Allegro tools ) in Git repository
- Circuit Schematic
- Users
- Software
- Firmware
Releases
Latest:*
- Hardware v1.0 - Manufacturing information. (Gerber, Drill files,BoM) PCB layout by ANS Industrial
- Firmware v1.0 - - point-to-firmware
Contacts
- David Cussans - University of Bristol
Status
| Date | Event |
|---|---|
| 01-07-2015 | Board available |
24 April 2016
