Renaming of hydra_ram

hdl/rtl/Manifest.py

-files = ['hydra_core.vhd']
+files = ['hydra_core.vhd', 'hydra_iram.vhd', 'hydra_dram.vhd']

hdl/rtl/hydra_core.vhd

@@ -158,7 +158,7 @@ begin
 
   im1_dm_en <= '1' when reg_dm_load = '1' and reg_dm_is_wishbone = '0' and reg_dm_addr (16) = '0' else '0';
 
-  inst_rom: entity work.hydra_ram
+  inst_iram: entity work.hydra_iram
     generic map (
       g_RAM_LOG_SIZE => g_IRAM_LOG_SIZE
     )

hdl/rtl/hydra_ram.vhd → hdl/rtl/hydra_iram.vhd

@@ -29,7 +29,7 @@ use ieee.numeric_std.all;
 
 use work.secded_32b_pkg.all;
 
-entity hydra_ram is
+entity hydra_iram is
   generic(
     g_RAM_LOG_SIZE : natural := 12);  --  In bytes
   port(
@@ -68,9 +68,9 @@ entity hydra_ram is
     --  Scrubber
     scrubber_period_i : in  std_logic_vector(15 downto 0)
   );
-end hydra_ram;
+end hydra_iram;
 
-architecture arch of hydra_ram is
+architecture arch of hydra_iram is
   constant RAM_WSIZE : natural := 2 ** (g_RAM_LOG_SIZE - 2);
   type t_ram39_type is array(natural range <>) of std_logic_vector(38 downto 0);