From c3f3ee6ddee1bebe5cb024c382cd7408b76e500b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tristan.gingold@cern.ch>
Date: Thu, 16 Dec 2021 10:29:40 +0100
Subject: [PATCH] Renaming of hydra_ram
---
hdl/rtl/Manifest.py | 2 +-
hdl/rtl/hydra_core.vhd | 2 +-
hdl/rtl/{hydra_ram.vhd => hydra_iram.vhd} | 6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
rename hdl/rtl/{hydra_ram.vhd => hydra_iram.vhd} (99%)
diff --git a/hdl/rtl/Manifest.py b/hdl/rtl/Manifest.py
index 4d111d8..55bd842 100644
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
@@ -1 +1 @@
-files = ['hydra_core.vhd']
+files = ['hydra_core.vhd', 'hydra_iram.vhd', 'hydra_dram.vhd']
diff --git a/hdl/rtl/hydra_core.vhd b/hdl/rtl/hydra_core.vhd
index 854da39..4a85d70 100644
--- a/hdl/rtl/hydra_core.vhd
+++ b/hdl/rtl/hydra_core.vhd
@@ -158,7 +158,7 @@ begin
im1_dm_en <= '1' when reg_dm_load = '1' and reg_dm_is_wishbone = '0' and reg_dm_addr (16) = '0' else '0';
- inst_rom: entity work.hydra_ram
+ inst_iram: entity work.hydra_iram
generic map (
g_RAM_LOG_SIZE => g_IRAM_LOG_SIZE
)
diff --git a/hdl/rtl/hydra_ram.vhd b/hdl/rtl/hydra_iram.vhd
similarity index 99%
rename from hdl/rtl/hydra_ram.vhd
rename to hdl/rtl/hydra_iram.vhd
index 5320988..f210747 100644
--- a/hdl/rtl/hydra_ram.vhd
+++ b/hdl/rtl/hydra_iram.vhd
@@ -29,7 +29,7 @@ use ieee.numeric_std.all;
use work.secded_32b_pkg.all;
-entity hydra_ram is
+entity hydra_iram is
generic(
g_RAM_LOG_SIZE : natural := 12); -- In bytes
port(
@@ -68,9 +68,9 @@ entity hydra_ram is
-- Scrubber
scrubber_period_i : in std_logic_vector(15 downto 0)
);
-end hydra_ram;
+end hydra_iram;
-architecture arch of hydra_ram is
+architecture arch of hydra_iram is
constant RAM_WSIZE : natural := 2 ** (g_RAM_LOG_SIZE - 2);
type t_ram39_type is array(natural range <>) of std_logic_vector(38 downto 0);
--
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