Automatically build mss, and add envm file

hdl/syn/sf2-test/Manifest.py

@@ -7,12 +7,13 @@ syn_grade = "STD"
 syn_package = "FG484"  # 484 FBGA
 syn_project = "sf2_test"
 
+syn_project_extra_files = [
+    'set_constraints.tcl', 'build_mss.tcl']
 
 top_module = "sf2_test"
 syn_tool = "liberosoc"
 
-# files = ['diot_wic_demo.pdc', 'diot_wic_demo.sdc']
 files = ['osc_comps.vhd', 'io.pdc',
-         'syn_clocks.sdc'] # , 'clocks.pdc']
+         'syn_clocks.sdc', 'pnr_clocks.sdc']
 
 modules = { "local" : [ "../../top/sf2-test"] }

hdl/syn/sf2-test/build_mss.tcl

+# configure and add MSS.
+create_and_configure_core -core_vlnv {Actel:SmartFusion2MSS:MSS:1.1.500} -component_name {mymss} -params {}
+mss_disable_instance -component_name {mymss} -instance_name {GPIO}
+mss_disable_instance -component_name {mymss} -instance_name {RTC}
+mss_disable_instance -component_name {mymss} -instance_name {MDDR}
+mss_disable_instance -component_name {mymss} -instance_name {USB}
+mss_disable_instance -component_name {mymss} -instance_name {MAC}
+mss_disable_instance -component_name {mymss} -instance_name {I2C_0}
+mss_disable_instance -component_name {mymss} -instance_name {I2C_1}
+mss_disable_instance -component_name {mymss} -instance_name {SPI_0}
+mss_disable_instance -component_name {mymss} -instance_name {SPI_1}
+mss_disable_instance -component_name {mymss} -instance_name {FIC32_1}
+mss_disable_instance -component_name {mymss} -instance_name {MMUART_1}
+mss_disable_instance -component_name {mymss} -instance_name {WATCHDOG}
+mss_disable_instance -component_name {mymss} -instance_name {DMA}
+
+mss_enable_instance -component_name {mymss} -instance_name {MMUART_0}
+mss_enable_instance -component_name {mymss} -instance_name {FIC32_0}
+
+mss_configure_instance -component_name {mymss} -instance_name {RESET} \
+    -params {"USER_MSS_RESET_N_USED:false" "FAB_M3_RESET_N_USED:true" "FPGA_RESET_N_USED:true"}
+mss_save_instance_config -component_name {mymss} -instance_name {RESET}
+
+mss_configure_instance -component_name {mymss} -instance_name {FIC32_0} \
+    -params {"INTERFACE_TYPE:INTERFACE_AHB" "USE_BYPASS_MODE:false" "INTERFACE_MASTER:false" "INTERFACE_SLAVE:1" "EXPOSE_MASTER_IDENTITY:false"}
+mss_save_instance_config -component_name {mymss} -instance_name {FIC32_0}
+
+mss_configure_envm -component_name {mymss} -cfg_file "./envm.cfg"
+
+generate_component -component_name {mymss} -recursive 0 
+
+build_design_hierarchy 

hdl/syn/sf2-test/envm.cfg

+nvm_set_data_storage_client \
+   -client_name {code}  \
+   -number_of_words 168 \
+   -word_size 8 \
+   -use_for_simulation {0}  \
+   -content_type {MEMORY_FILE}  \
+   -memory_file_format {BINARY}  \
+   -memory_file {../../../../sw/sf2-test/main.mem}  \
+   -base_address 0 \
+   -reprogram 1 \
+   -use_as_rom 1 \
+   -lock_address 0

hdl/syn/sf2-test/exported.tcl

-# Microsemi Tcl Script
-# libero
-# Date: Fri Nov 26 11:17:26 2021
-# Directory /home/tgingold/Repositories/ohwr/diot-radtol-base/hdl/syn/sf2-test
-# File /home/tgingold/Repositories/ohwr/diot-radtol-base/hdl/syn/sf2-test/exported.tcl
-
-
-open_project -file {./sf2_test/sf2_test.prjx} -do_backup_on_convert 1 -backup_file {./sf2_test.zip} 
-run_tool -name {CONSTRAINT_MANAGEMENT} 
-organize_tool_files -tool {PLACEROUTE} -file {./io.pdc} -module {sf2_test::work} -input_type {constraint} 
-organize_tool_files -tool {VERIFYTIMING} -file {} -module {sf2_test::work} -input_type {constraint} 
-create_links \
-         -convert_EDN_to_HDL 0 \
-         -sdc {./pnr_clocks.sdc} 
-organize_tool_files -tool {PLACEROUTE} -file {./io.pdc} -file {./pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint} 
-organize_tool_files -tool {VERIFYTIMING} -file {./pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint} 
-unlink_files -file {./clocks.sdc} 
-create_links \
-         -convert_EDN_to_HDL 0 \
-         -sdc {./syn_clocks.sdc} 
-organize_tool_files -tool {SYNTHESIZE} -file {./syn_clocks.sdc} -module {sf2_test::work} -input_type {constraint} 
-delete_files -file {./sf2_test/synthesis/sf2_test.vm} -from_disk 
-clean_tool -name {SYNTHESIZE} 
-run_tool -name {SYNTHESIZE} 
-run_tool -name {PLACEROUTE} 

hdl/syn/sf2-test/io.pdc

@@ -23,7 +23,7 @@ set_io led2_o       \
     -DIRECTION OUTPUT
 
     
-set_io but_i          \
+# set_io but_i          \
     -pinname U19      \
     -fixed yes        \
     -RES_PULL Up      \

hdl/syn/sf2-test/set_constraints.tcl

+# Re-organize constraint files
+organize_tool_files -tool {SYNTHESIZE} -file {syn_clocks.sdc} -module {sf2_test::work} -input_type {constraint}
+organize_tool_files -tool {PLACEROUTE} -file {io.pdc} -file {pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint} 
+organize_tool_files -tool {VERIFYTIMING} -file {pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint} 

hdl/top/sf2-test/Manifest.py

 files = ['sf2_test.vhd', 'uart.vhd',
-         'uart_MSS.vhd', 'uart_MSS_syn.vhd',
+#         'uart_MSS.vhd', 'uart_MSS_syn.vhd',
          'OSC_C0.vhd', 'OSC_C0_OSC_C0_0_OSC.vhd',
          'FCCC_C0.vhd', 'FCCC_C0_FCCC_C0_0_FCCC.vhd']
 

hdl/top/sf2-test/uart.vhd

@@ -173,7 +173,7 @@ SYSRESET_0 : SYSRESET
         POWER_ON_RESET_N => POWER_ON_RESET_N_net_0 
         );
 -- uart_MSS_0
-uart_MSS_0 : uart_MSS
+uart_MSS_0 : entity work.mymss -- entity work.mymss_MSS --uart_MSS -- 
     port map( 
         -- Inputs
         MCCC_CLK_BASE         => clk_100_net_0,