From abb5b4dfe0a1a8cd2c6a3217d9d61b2298c019c0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tristan.gingold@cern.ch>
Date: Tue, 30 Nov 2021 13:26:15 +0100
Subject: [PATCH] Automatically build mss, and add envm file
---
hdl/syn/sf2-test/Manifest.py | 5 +++--
hdl/syn/sf2-test/build_mss.tcl | 32 ++++++++++++++++++++++++++++
hdl/syn/sf2-test/envm.cfg | 12 +++++++++++
hdl/syn/sf2-test/exported.tcl | 25 ----------------------
hdl/syn/sf2-test/io.pdc | 2 +-
hdl/syn/sf2-test/set_constraints.tcl | 4 ++++
hdl/top/sf2-test/Manifest.py | 2 +-
hdl/top/sf2-test/uart.vhd | 2 +-
8 files changed, 54 insertions(+), 30 deletions(-)
create mode 100644 hdl/syn/sf2-test/build_mss.tcl
create mode 100644 hdl/syn/sf2-test/envm.cfg
delete mode 100644 hdl/syn/sf2-test/exported.tcl
create mode 100644 hdl/syn/sf2-test/set_constraints.tcl
diff --git a/hdl/syn/sf2-test/Manifest.py b/hdl/syn/sf2-test/Manifest.py
index 8402e01..cd33587 100644
--- a/hdl/syn/sf2-test/Manifest.py
+++ b/hdl/syn/sf2-test/Manifest.py
@@ -7,12 +7,13 @@ syn_grade = "STD"
syn_package = "FG484" # 484 FBGA
syn_project = "sf2_test"
+syn_project_extra_files = [
+ 'set_constraints.tcl', 'build_mss.tcl']
top_module = "sf2_test"
syn_tool = "liberosoc"
-# files = ['diot_wic_demo.pdc', 'diot_wic_demo.sdc']
files = ['osc_comps.vhd', 'io.pdc',
- 'syn_clocks.sdc'] # , 'clocks.pdc']
+ 'syn_clocks.sdc', 'pnr_clocks.sdc']
modules = { "local" : [ "../../top/sf2-test"] }
diff --git a/hdl/syn/sf2-test/build_mss.tcl b/hdl/syn/sf2-test/build_mss.tcl
new file mode 100644
index 0000000..264e1d0
--- /dev/null
+++ b/hdl/syn/sf2-test/build_mss.tcl
@@ -0,0 +1,32 @@
+# configure and add MSS.
+create_and_configure_core -core_vlnv {Actel:SmartFusion2MSS:MSS:1.1.500} -component_name {mymss} -params {}
+mss_disable_instance -component_name {mymss} -instance_name {GPIO}
+mss_disable_instance -component_name {mymss} -instance_name {RTC}
+mss_disable_instance -component_name {mymss} -instance_name {MDDR}
+mss_disable_instance -component_name {mymss} -instance_name {USB}
+mss_disable_instance -component_name {mymss} -instance_name {MAC}
+mss_disable_instance -component_name {mymss} -instance_name {I2C_0}
+mss_disable_instance -component_name {mymss} -instance_name {I2C_1}
+mss_disable_instance -component_name {mymss} -instance_name {SPI_0}
+mss_disable_instance -component_name {mymss} -instance_name {SPI_1}
+mss_disable_instance -component_name {mymss} -instance_name {FIC32_1}
+mss_disable_instance -component_name {mymss} -instance_name {MMUART_1}
+mss_disable_instance -component_name {mymss} -instance_name {WATCHDOG}
+mss_disable_instance -component_name {mymss} -instance_name {DMA}
+
+mss_enable_instance -component_name {mymss} -instance_name {MMUART_0}
+mss_enable_instance -component_name {mymss} -instance_name {FIC32_0}
+
+mss_configure_instance -component_name {mymss} -instance_name {RESET} \
+ -params {"USER_MSS_RESET_N_USED:false" "FAB_M3_RESET_N_USED:true" "FPGA_RESET_N_USED:true"}
+mss_save_instance_config -component_name {mymss} -instance_name {RESET}
+
+mss_configure_instance -component_name {mymss} -instance_name {FIC32_0} \
+ -params {"INTERFACE_TYPE:INTERFACE_AHB" "USE_BYPASS_MODE:false" "INTERFACE_MASTER:false" "INTERFACE_SLAVE:1" "EXPOSE_MASTER_IDENTITY:false"}
+mss_save_instance_config -component_name {mymss} -instance_name {FIC32_0}
+
+mss_configure_envm -component_name {mymss} -cfg_file "./envm.cfg"
+
+generate_component -component_name {mymss} -recursive 0
+
+build_design_hierarchy
diff --git a/hdl/syn/sf2-test/envm.cfg b/hdl/syn/sf2-test/envm.cfg
new file mode 100644
index 0000000..1d04cd5
--- /dev/null
+++ b/hdl/syn/sf2-test/envm.cfg
@@ -0,0 +1,12 @@
+nvm_set_data_storage_client \
+ -client_name {code} \
+ -number_of_words 168 \
+ -word_size 8 \
+ -use_for_simulation {0} \
+ -content_type {MEMORY_FILE} \
+ -memory_file_format {BINARY} \
+ -memory_file {../../../../sw/sf2-test/main.mem} \
+ -base_address 0 \
+ -reprogram 1 \
+ -use_as_rom 1 \
+ -lock_address 0
diff --git a/hdl/syn/sf2-test/exported.tcl b/hdl/syn/sf2-test/exported.tcl
deleted file mode 100644
index d004b96..0000000
--- a/hdl/syn/sf2-test/exported.tcl
+++ /dev/null
@@ -1,25 +0,0 @@
-# Microsemi Tcl Script
-# libero
-# Date: Fri Nov 26 11:17:26 2021
-# Directory /home/tgingold/Repositories/ohwr/diot-radtol-base/hdl/syn/sf2-test
-# File /home/tgingold/Repositories/ohwr/diot-radtol-base/hdl/syn/sf2-test/exported.tcl
-
-
-open_project -file {./sf2_test/sf2_test.prjx} -do_backup_on_convert 1 -backup_file {./sf2_test.zip}
-run_tool -name {CONSTRAINT_MANAGEMENT}
-organize_tool_files -tool {PLACEROUTE} -file {./io.pdc} -module {sf2_test::work} -input_type {constraint}
-organize_tool_files -tool {VERIFYTIMING} -file {} -module {sf2_test::work} -input_type {constraint}
-create_links \
- -convert_EDN_to_HDL 0 \
- -sdc {./pnr_clocks.sdc}
-organize_tool_files -tool {PLACEROUTE} -file {./io.pdc} -file {./pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint}
-organize_tool_files -tool {VERIFYTIMING} -file {./pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint}
-unlink_files -file {./clocks.sdc}
-create_links \
- -convert_EDN_to_HDL 0 \
- -sdc {./syn_clocks.sdc}
-organize_tool_files -tool {SYNTHESIZE} -file {./syn_clocks.sdc} -module {sf2_test::work} -input_type {constraint}
-delete_files -file {./sf2_test/synthesis/sf2_test.vm} -from_disk
-clean_tool -name {SYNTHESIZE}
-run_tool -name {SYNTHESIZE}
-run_tool -name {PLACEROUTE}
diff --git a/hdl/syn/sf2-test/io.pdc b/hdl/syn/sf2-test/io.pdc
index 8660f06..b52b209 100644
--- a/hdl/syn/sf2-test/io.pdc
+++ b/hdl/syn/sf2-test/io.pdc
@@ -23,7 +23,7 @@ set_io led2_o \
-DIRECTION OUTPUT
-set_io but_i \
+# set_io but_i \
-pinname U19 \
-fixed yes \
-RES_PULL Up \
diff --git a/hdl/syn/sf2-test/set_constraints.tcl b/hdl/syn/sf2-test/set_constraints.tcl
new file mode 100644
index 0000000..5d9173c
--- /dev/null
+++ b/hdl/syn/sf2-test/set_constraints.tcl
@@ -0,0 +1,4 @@
+# Re-organize constraint files
+organize_tool_files -tool {SYNTHESIZE} -file {syn_clocks.sdc} -module {sf2_test::work} -input_type {constraint}
+organize_tool_files -tool {PLACEROUTE} -file {io.pdc} -file {pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint}
+organize_tool_files -tool {VERIFYTIMING} -file {pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint}
diff --git a/hdl/top/sf2-test/Manifest.py b/hdl/top/sf2-test/Manifest.py
index f283ae4..ac69a13 100644
--- a/hdl/top/sf2-test/Manifest.py
+++ b/hdl/top/sf2-test/Manifest.py
@@ -1,5 +1,5 @@
files = ['sf2_test.vhd', 'uart.vhd',
- 'uart_MSS.vhd', 'uart_MSS_syn.vhd',
+# 'uart_MSS.vhd', 'uart_MSS_syn.vhd',
'OSC_C0.vhd', 'OSC_C0_OSC_C0_0_OSC.vhd',
'FCCC_C0.vhd', 'FCCC_C0_FCCC_C0_0_FCCC.vhd']
diff --git a/hdl/top/sf2-test/uart.vhd b/hdl/top/sf2-test/uart.vhd
index c08220c..1f5436f 100644
--- a/hdl/top/sf2-test/uart.vhd
+++ b/hdl/top/sf2-test/uart.vhd
@@ -173,7 +173,7 @@ SYSRESET_0 : SYSRESET
POWER_ON_RESET_N => POWER_ON_RESET_N_net_0
);
-- uart_MSS_0
-uart_MSS_0 : uart_MSS
+uart_MSS_0 : entity work.mymss -- entity work.mymss_MSS --uart_MSS --
port map(
-- Inputs
MCCC_CLK_BASE => clk_100_net_0,
--
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