As an example I will describe White Rabbit Cores, which is a part of
White Rabbit project. Hdlmake is there engaged in the synthesis
makefiles generation. It is synthesized with ISE.
Before going further it is recommended to clone WRC git repository
(git@ohwr.org:hdl-core-lib/wr-cores.git).
Open the cloned project and go to syn/spec_1_1/wr_core_demo. Its a directory, where the main project file and the corresponding Manifest is kept. Let's analyze what can be found in the manifest:
target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_top_wrc.xise"
modules = { "local" : [ "../../../top/spec_1_1/wr_core_demo" ] }| Variable | Value | Meaning |
| target | xilinx | Target vendor for the synthesis is Xilinx |
| action | synthesis | Action for the makefile is synthesis |
| fetchto | ./../../ip_cores | All fetched modules from the current manifest will be put in ../../../ip_cores |
| syn_device | xc6slx45t | Part number to but put in the project file |
| syn_grade | -3 | |
| syn_package | fgg484 | Package of the chosen part |
| syn_top | spec_top | Top design's entity |
| syn_project | spec_top_wrc.xise | ISE p |